Inventor · disambiguated record
Kevin R. Iadonato
Also filed as: IADONATO KEVIN · IADONATO KEVIN R · IADONATO KEVIN RAY
38 granted patents·1 pending application·989 citations·filing 1992–2009
98Inventor score
Technology areasG06F
Files withSEIKO EPSON CORP29TRANSMETA CORP3HITACHI MICRO SYSTEMS INC2GARG SANJIV1HITACHI AMERICA LTD1
Top patents by PatentIndex Score
39 records- 0194US8074052B2System and method for assigning tags to control instruction processing in a superscalar processorIADONATO KEVIN R·Filed 2008·Granted Dec 6, 2011·37 cites·18 claims
- 0293US5497499ASuperscalar risc instruction schedulingSEIKO EPSON CORP·Filed 1994·Granted Mar 5, 1996·120 cites·16 claims
- 0389US6360309B1System and method for assigning tags to control instruction processing in a superscalar processorSEIKO EPSON CORP·Filed 2000·Granted Mar 19, 2002·36 cites·18 claims
- 0485US7558945B2System and method for register renamingSEIKO EPSON CORP·Filed 2005·Granted Jul 7, 2009·8 cites·24 claims
- 0585US7051187B2Superscalar RISC instruction schedulingTRANSMETA CORP·Filed 2002·Granted May 23, 2006·24 cites·19 claims
- 0684US7174525B2Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chipSEIKO EPSON CORP·Filed 2004·Granted Feb 6, 2007·21 cites·8 claims
- 0784US6782521B2Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chipSEIKO EPSON CORP·Filed 2002·Granted Aug 24, 2004·21 cites·7 claims
- 0884US5371684ASemiconductor floor plan for a register renaming circuitSEIKO EPSON CORP·Filed 1992·Granted Dec 6, 1994·63 cites·1 claims
- 0983US5590295ASystem and method for register renamingSEIKO EPSON CORP·Filed 1995·Granted Dec 31, 1996·66 cites·17 claims
- 1082US6757808B2System and method for assigning tags to control instruction processing in a superscalar processorSEIKO EPSON CORP·Filed 2002·Granted Jun 29, 2004·19 cites·20 claims
- 1182US6401232B1Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chipSEIKO EPSON CORP·Filed 2000·Granted Jun 4, 2002·19 cites·5 claims
- 1280US7979678B2System and method for register renamingSEIKO EPSON CORP·Filed 2009·Granted Jul 12, 2011·5 cites·34 claims
- 1378US5737624ASuperscalar risc instruction schedulingSEIKO EPSON CORP·Filed 1996·Granted Apr 7, 1998·51 cites·19 claims
- 1477US7043624B2System and method for assigning tags to control instruction processing in a superscalar processorSEIKO EPSON CORP·Filed 2004·Granted May 9, 2006·13 cites·18 claims
- 1577US5604912ASystem and method for assigning tags to instructions to control instruction executionSEIKO EPSON CORP·Filed 1992·Granted Feb 18, 1997·62 cites·40 claims
- 1676US6922772B2System and method for register renamingSEIKO EPSON CORP·Filed 2002·Granted Jul 26, 2005·12 cites·9 claims
- 1776US6408375B2System and method for register renamingSEIKO EPSON CORP·Filed 2001·Granted Jun 18, 2002·13 cites·19 claims
- 1876US5860000AFloating point unit pipeline synchronized with processor pipelineHITACHI MICRO SYSTEMS INC·Filed 1996·Granted Jan 12, 1999·55 cites·8 claims
- 1975US6970995B2System and method for register renamingSEIKO EPSON CORP·Filed 2002·Granted Nov 29, 2005·12 cites·9 claims
- 2072US5628021ASystem and method for assigning tags to control instruction processing in a superscalar processorSEIKO EPSON CORP·Filed 1994·Granted May 6, 1997·34 cites·62 claims
- 2169US7430651B2System and method for assigning tags to control instruction processing in a superscalar processorSEIKO EPSON CORP·Filed 2006·Granted Sep 30, 2008·2 cites·20 claims
- 2268US7802074B2Superscalar RISC instruction schedulingGARG SANJIV·Filed 2007·Granted Sep 21, 2010·2 cites·18 claims
- 2368US5896542ASystem and method for assigning tags to control instruction processing in a superscalar processorSEIKO EPSON CORP·Filed 1997·Granted Apr 20, 1999·30 cites·34 claims
- 2466US6772327B2Floating point unit pipeline synchronized with processor pipelineHITACHI MICRO SYSTEMS INC·Filed 2002·Granted Aug 3, 2004·8 cites·26 claims
- 2566US5734584AIntegrated structure layout and layout of interconnections for an integrated circuit chipSEIKO EPSON CORP·Filed 1996·Granted Mar 31, 1998·27 cites·3 claims
- 2665US5809276ASystem and method for register renamingSEIKO EPSON CORP·Filed 1996·Granted Sep 15, 1998·26 cites·17 claims
- 2764US6289433B1Superscalar RISC instruction schedulingTRANSMETA CORP·Filed 1999·Granted Sep 11, 2001·26 cites·19 claims
- 2864US6138231ASystem and method for register renamingSEIKO EPSON CORP·Filed 1998·Granted Oct 24, 2000·24 cites·43 claims
- 2964US5566385AIntegrated structure layout and layout of interconnections for an integrated circuit chipSEIKO EPSON CORP·Filed 1994·Granted Oct 15, 1996·22 cites·4 claims
- 3062US6092176ASystem and method for assigning tags to control instruction processing in a superscalar processorSEIKO EPSON CORP·Filed 1999·Granted Jul 18, 2000·22 cites·20 claims
- 3162US5831871AIntegrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chipSEIKO EPSON CORP·Filed 1997·Granted Nov 3, 1998·21 cites·5 claims
- 3261US6272617B1System and method for register renamingSEIKO EPSON CORP·Filed 1999·Granted Aug 7, 2001·21 cites·29 claims
- 3361US5974526ASuperscalar RISC instruction schedulingSEIKO CORP·Filed 1997·Granted Oct 26, 1999·23 cites·34 claims
- 3458US6083274AIntegrated structure layout and layout of interconnections for an integrated circuit chipSEIKO EPSON CORP·Filed 1998·Granted Jul 4, 2000·18 cites·7 claims
- 3556US7162616B2Floating point unit pipeline synchronized with processor pipelineRENESAS TECHNOLOGY AMERICA INC·Filed 2004·Granted Jan 9, 2007·3 cites·2 claims
- 3654US7555738B2Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chipSEIKO EPSON CORP·Filed 2007·Granted Jun 30, 2009·0 cites·9 claims
- 3752US5892963ASystem and method for assigning tags to instructions to control instruction executionSEIKO EPSON CORP·Filed 1997·Granted Apr 6, 1999·22 cites·30 claims
- 3851US2006041736A1Superscalar RISC instruction schedulingTRANSMETA CORP·Filed 2005·Application pending·0 cites
- 3930US6418528B1Floating point unit pipeline synchronized with processor pipelineHITACHI AMERICA LTD·Filed 1998·Granted Jul 9, 2002·1 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →