Superscalar RISC instruction scheduling

Abstract

A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.

1 . A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands, the system comprising: 
 (a) data dependance check means for determining data dependencies between the instructions;    (b) tag assignment means for generating one or more tags to specify the location of operands, based on said data dependencies determined by said data dependance check means; and    (c) register file port means for selecting said tags generated by said tag assignment means and passing said tags onto the read address ports of the register file for storing execution results.