Inventor · disambiguated record
Peter Wung Lee
Also filed as: LEE PETER · LEE PETER W · LEE PETER WUNG
191 granted patents·19 pending applications·5,615 citations·filing 1984–2019
99Inventor score
Files withAPLUS FLASH TECHNOLOGY INC86LEE PETER WUNG41MARVELL INT LTD24MARVELL WORLD TRADE LTD19APLUS INTEGRATED CIRCUITS INC18
Top patents by PatentIndex Score
210 records- 0198US9171627B2Non-boosting program inhibit scheme in NAND designAPLUS FLASH TECHNOLOGY INC·Filed 2013·Granted Oct 27, 2015·44 cites·33 claims
- 0298US7164608B2NVRAM memory cell architecture that integrates conventional SRAM and flash cellsAPLUS FLASH TECHNOLOGY INC·Filed 2005·Granted Jan 16, 2007·375 cites·24 claims
- 0398US6862223B1Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2002·Granted Mar 1, 2005·130 cites·28 claims
- 0498US6714457B1Parallel channel programming scheme for MLC flash memoryAPLUS FLASH TECHNOLOGY INC·Filed 2002·Granted Mar 30, 2004·164 cites·36 claims
- 0598US5768193ABit-refreshable method and circuit for refreshing a nonvolatile flash memoryAPLUS INTEGRATED CIRCUITS INC·Filed 1996·Granted Jun 16, 1998·207 cites·19 claims
- 0697US8773903B2High speed high density nand-based 2T-NOR flash memory designLEE PETER WUNG·Filed 2012·Granted Jul 8, 2014·33 cites·33 claims
- 0797US8120959B2NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating sameLEE PETER WUNG·Filed 2009·Granted Feb 21, 2012·73 cites·56 claims
- 0897US7369438B2Combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applicationsAPLUS FLASH TECHNOLOGY INC·Filed 2005·Granted May 6, 2008·65 cites·71 claims
- 0997US7102929B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2005·Granted Sep 5, 2006·51 cites·5 claims
- 1096US9666286B2Self-timed SLC NAND pipeline and concurrent program without verificationLEE PETER WUNG·Filed 2015·Granted May 30, 2017·25 cites·46 claims
- 1196US6620682B1Set of three level concurrent word line bias conditions for a nor type flash memory arrayAPLUS FLASH TECHNOLOGY INC·Filed 2001·Granted Sep 16, 2003·110 cites·8 claims
- 1296US5953255ALow voltage, low current hot-hole injection erase and hot-electron programmable flash memory with enhanced enduranceAPLUS FLASH TECHNOLOGY INC·Filed 1997·Granted Sep 14, 1999·176 cites·20 claims
- 1396US5822252AFlash memory wordline decoder with overerase repairAPLUS INTEGRATED CIRCUITS INC·Filed 1996·Granted Oct 13, 1998·181 cites·28 claims
- 1496US5748538AOR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell arrayAPLUS INTEGRATED CIRCUITS INC·Filed 1996·Granted May 5, 1998·182 cites·10 claims
- 1595US7609538B1Logic process DRAMMARVELL INT LTD·Filed 2006·Granted Oct 27, 2009·26 cites·30 claims
- 1695US7110302B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2005·Granted Sep 19, 2006·25 cites·52 claims
- 1795US7075826B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2005·Granted Jul 11, 2006·28 cites·8 claims
- 1895US6850438B2Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operationsAPLUS FLASH TECHNOLOGY INC·Filed 2003·Granted Feb 1, 2005·75 cites·23 claims
- 1995US6556481B13-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cellAPLUS FLASH TECHNOLOGY INC·Filed 2001·Granted Apr 29, 2003·114 cites·22 claims
- 2095US5978283ACharge pump circuitsAPLUS FLASH TECHNOLOGY INC·Filed 1998·Granted Nov 2, 1999·147 cites·18 claims
- 2194US9613704B22D/3D NAND memory array with bit-line hierarchical structure for multi-page concurrent SLC/MLC program and program-verifyAPLUS FLASH TECH INC·Filed 2014·Granted Apr 4, 2017·37 cites·124 claims
- 2294US7087953B2Unified non-volatile memory device and method for integrating NOR and NAND-type flash memory and EEPROM device on a single substrateAPLUS FLASH TECHNOLOGY INC·Filed 2005·Granted Aug 8, 2006·23 cites·21 claims
- 2394US6757196B1Two transistor flash memory cell for use in EEPROM arrays with a programmable logic deviceAPLUS FLASH TECHNOLOGY INC·Filed 2001·Granted Jun 29, 2004·83 cites·39 claims
- 2494US5835420ANode-precise voltage regulation for a MOS memory systemAPLUS FLASH TECHNOLOGY INC·Filed 1997·Granted Nov 10, 1998·104 cites·34 claims
- 2594US5748545AMemory device with on-chip manufacturing and memory cell defect detection capabilityAPLUS INTEGRATED CIRCUITS INC·Filed 1997·Granted May 5, 1998·116 cites·40 claims
- 2693US9443579B2VSL-based VT-compensation and analog program scheme for NAND array without CSLLEE PETER WUNG·Filed 2015·Granted Sep 13, 2016·16 cites·57 claims
- 2793US9019764B2Low-voltage page buffer to be used in NVM designAPLUS FLASH TECHNOLOGY INC·Filed 2012·Granted Apr 28, 2015·17 cites·23 claims
- 2893US8120966B2Method and apparatus for management of over-erasure in NAND-based NOR-type flash memoryLEE PETER WUNG·Filed 2010·Granted Feb 21, 2012·19 cites·71 claims
- 2993US7830713B2Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash arrayAPLUS FLASH TECHNOLOGY INC·Filed 2008·Granted Nov 9, 2010·25 cites·48 claims
- 3093US7324384B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2006·Granted Jan 29, 2008·18 cites·20 claims
- 3193US6498752B1Three step write process used for a nonvolatile NOR type EEPROM memoryAPLUS FLASH TECHNOLOGY INC·Filed 2001·Granted Dec 24, 2002·83 cites·39 claims
- 3293US6381670B1Flash memory array having maximum and minimum threshold voltage detection for eliminating over-erasure problem and enhancing write operationAPLUS FLASH TECHNOLOGY INC·Filed 1997·Granted Apr 30, 2002·147 cites·43 claims
- 3392US9659636B2NAND memory array with BL-hierarchical structure for concurrent all-BL, all-threshold-state program, and alternative-WL program, odd/even read and verify operationsLEE PETER WUNG·Filed 2015·Granted May 23, 2017·14 cites·134 claims
- 3492US9595319B2Partial/full array/block erase for 2D/3D hierarchical NANDLEE PETER WUNG·Filed 2016·Granted Mar 14, 2017·13 cites·59 claims
- 3592US9263137B2NAND array architecture for multiple simutaneous program and readAPLUS FLASH TECHNOLOGY INC·Filed 2014·Granted Feb 16, 2016·12 cites·17 claims
- 3692US6788612B2Flash memory array structure suitable for multiple simultaneous operationsAPLUS FLASH TECHNOLOGY INC·Filed 2003·Granted Sep 7, 2004·50 cites·9 claims
- 3792US6023188APositive/negative high voltage charge pump systemAPLUS FLASH TECHNOLOGY INC·Filed 1999·Granted Feb 8, 2000·101 cites·20 claims
- 3892US6009022ANode-precise voltage regulation for a MOS memory systemAPLUS FLASH TECHNOLOGY INC·Filed 1998·Granted Dec 28, 1999·83 cites·20 claims
- 3991US9230677B2NAND array hiarchical BL structures for multiple-WL and all-BL simultaneous erase, erase-verify, program, program-verify, and read operationsAPLUS FLASH TECHNOLOGY INC·Filed 2014·Granted Jan 5, 2016·12 cites·73 claims
- 4091US8335108B2Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash arrayLEE PETER WUNG·Filed 2008·Granted Dec 18, 2012·19 cites·28 claims
- 4191US8289775B2Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cells in an arrayLEE PETER WUNG·Filed 2009·Granted Oct 16, 2012·24 cites·77 claims
- 4291US8030128B1Method to form high density phase change memory (PCM) top contact every two bitsMARVELL INT LTD·Filed 2008·Granted Oct 4, 2011·21 cites·22 claims
- 4391US7636252B2Nonvolatile memory with a unified cell structureLEE PETER W·Filed 2006·Granted Dec 22, 2009·17 cites·20 claims
- 4491US7289366B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2006·Granted Oct 30, 2007·19 cites·40 claims
- 4591US7120064B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2005·Granted Oct 10, 2006·15 cites·20 claims
- 4691US5930826AFlash memory protection attribute status bits held in a flash memory arrayAPLUS INTEGRATED CIRCUITS INC·Filed 1997·Granted Jul 27, 1999·94 cites·12 claims
- 4791US5777923AFlash memory read/write controllerAPLUS INTEGRATED CIRCUITS INC·Filed 1996·Granted Jul 7, 1998·79 cites·22 claims
- 4890US8923049B21T1b and 2T2b flash-based, data-oriented EEPROM designAPLUS FLASH TECHNOLOGY INC·Filed 2013·Granted Dec 30, 2014·11 cites·45 claims
- 4990US8455923B2Embedded NOR flash memory process with NAND cell and true logic compatible low voltage deviceLEE PETER WUNG·Filed 2011·Granted Jun 4, 2013·10 cites·66 claims
- 5090US8072811B2NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory arrayLEE PETER WUNG·Filed 2009·Granted Dec 6, 2011·18 cites·92 claims
Showing the top 50 of 210 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →