Inventor · disambiguated record
Hien Boon Tan
Also filed as: TAN HIEN BOON
18 granted patents·5 pending applications·453 citations·filing 1999–2016
94Inventor score
Technology areasH10W
Files withUNITED TEST & ASSEMBLY CT LTD10UNITED TEST & ASSEMBLY CT LT2UNITED TEST AND ASSEMBLY TEST2UTAC UNITED TEST AND ASSEMBLY2RETUTA DANNY1
Top patents by PatentIndex Score
23 records- 0194US6420779B1Leadframe based chip scale package and method of producing the sameST ASSEMBLY TEST SERVICES LTD·Filed 1999·Granted Jul 16, 2002·263 cites·8 claims
- 0291US7323769B2High performance chip scale leadframe package with thermal dissipating structure and annular element and method of manufacturing packageUNITED TEST & ASSEMBLY CT LTD·Filed 2006·Granted Jan 29, 2008·28 cites·20 claims
- 0388US6630373B2Ground plane for exposed packageST ASSEMBLY TEST SERVICE LTD·Filed 2002·Granted Oct 7, 2003·46 cites·15 claims
- 0486US7375416B2Leadframe enhancement and method of producing a multi-row semiconductor packageUNITED TEST & ASSEMBLY CT LTD·Filed 2006·Granted May 20, 2008·15 cites·9 claims
- 0586US7339278B2Cavity chip packageUNITED TEST & ASSEMBLY CT LTD·Filed 2006·Granted Mar 4, 2008·21 cites·23 claims
- 0683US6876069B2Ground plane for exposed packageST ASSEMBLY TEST SERVICES PTE·Filed 2003·Granted Apr 5, 2005·36 cites·17 claims
- 0769US7723833B2Stacked die packagesUNITED TEST & ASSEMBLY CT LTD·Filed 2007·Granted May 25, 2010·5 cites·18 claims
- 0867US7345357B2High density chip scale leadframe package and method of manufacturing the packageUNITED TEST & ASSEMBLY CT LTD·Filed 2005·Granted Mar 18, 2008·3 cites·7 claims
- 0965US7830006B2Structurally-enhanced integrated circuit package and method of manufactureUNITED TEST & ASSEMBLY CT LTD·Filed 2005·Granted Nov 9, 2010·4 cites·10 claims
- 1062US7476569B2Leadframe enhancement and method of producing a multi-row semiconductor packageUNITED TEST & ASSEMBLY CT LTD·Filed 2008·Granted Jan 13, 2009·2 cites·7 claims
- 1161US8129222B2High density chip scale leadframe package and method of manufacturing the packageTAN HIEN BOON·Filed 2003·Granted Mar 6, 2012·11 cites·2 claims
- 1259US8030768B2Semiconductor package with under bump metallization aligned with open viasUNITED TEST & ASSEMBLY CT LT·Filed 2008·Granted Oct 4, 2011·2 cites·19 claims
- 1358US7816775B2Multi-die IC package and manufacturing methodUNITED TEST & ASSEMBLY CT LTD·Filed 2005·Granted Oct 19, 2010·2 cites·14 claims
- 1455US8039951B2Thermally enhanced semiconductor package and method of producing the sameUNITED TEST & ASSEMBLY CT LT·Filed 2006·Granted Oct 18, 2011·2 cites·9 claims
- 1552US7109570B2Integrated circuit package with leadframe enhancement and method of manufacturing the sameUNITED TEST AND ASSEMBLY TEST·Filed 2004·Granted Sep 19, 2006·12 cites·6 claims
- 1646US7678610B2Semiconductor chip package and method of manufactureUTAC UNITED TEST AND ASSEMBLY·Filed 2005·Granted Mar 16, 2010·1 cites·10 claims
- 1745US9842792B2Method of producing a semiconductor packageUNITED TEST AND ASSEMBLY CENTER LTD·Filed 2016·Granted Dec 12, 2017·0 cites·17 claims
- 1843US2009236726A1Package-on-package semiconductor structureUNITED TEST & ASSEMBLY CT LTD·Filed 2008·Application pending·0 cites
- 1940US9281218B2Method of producing a semiconductor packageRETUTA DANNY·Filed 2007·Granted Mar 8, 2016·0 cites·19 claims
- 2038US2008251938A1Semiconductor chip package and method of manufactureUTAC UNITED TEST AND ASSEMBLY·Filed 2008·Application pending·0 cites
- 2134US2008290509A1Chip Scale Package and Method of Assembling the SameUNITED TEST AND ASSEMBLY CT·Filed 2004·Application pending·0 cites
- 2233US2007132081A1Multiple stacked die window csp package and method of manufactureUNITED TEST & ASSEMBLY CT LTD·Filed 2005·Application pending·0 cites
- 2333US2004124508A1High performance chip scale leadframe package and method of manufacturing the packageUNITED TEST AND ASSEMBLY TEST·Filed 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →