Inventor · disambiguated record
Edward R. Prack
Also filed as: PRACK EDWARD · PRACK EDWARD R · PRACK EDWARD RUDOLPH
38 granted patents·8 pending applications·954 citations·filing 2000–2018
97Inventor score
Files withINTEL CORP21SHENZHEN XIUYUAN ELECTRONIC TECH CO LTD5FREESCALE SEMICONDUCTOR INC4ARANA LEONEL R2DIAS RAJENDRA C2
Top patents by PatentIndex Score
46 records- 0198US6921975B2Circuit device with at least partial packaging, exposed active surface and a voltage reference planeFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Jul 26, 2005·233 cites·23 claims
- 0298US6838776B2Circuit device with at least partial packaging and method for formingFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Jan 4, 2005·314 cites·43 claims
- 0397US8987918B2Interconnect structures with polymer coreINTEL CORP·Filed 2013·Granted Mar 24, 2015·54 cites·25 claims
- 0497US7361987B2Circuit device with at least partial packaging and method for formingFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Apr 22, 2008·75 cites·15 claims
- 0596US7428138B2Forming carbon nanotube capacitorsINTEL CORP·Filed 2005·Granted Sep 23, 2008·31 cites·10 claims
- 0696US6646347B2Semiconductor power device and method of formationMOTOROLA INC·Filed 2001·Granted Nov 11, 2003·137 cites·10 claims
- 0791US9508667B2Formation of solder and copper interconnect structures and associated techniques and configurationsINTEL CORP·Filed 2014·Granted Nov 29, 2016·10 cites·4 claims
- 0888US7462551B2Adhesive system for supporting thin silicon waferINTEL CORP·Filed 2005·Granted Dec 9, 2008·17 cites·5 claims
- 0987US8466559B2Forming die backside coating structures with coreless packagesMANEPALLI RAHUL N·Filed 2010·Granted Jun 18, 2013·9 cites·17 claims
- 1086US10068863B2Formation of solder and copper interconnect structures and associated techniques and configurationsINTEL CORP·Filed 2016·Granted Sep 4, 2018·4 cites·5 claims
- 1181US10615151B2Integrated circuit multichip stacked packaging structure and methodSHENZHEN XIUYUAN ELECTRONIC TECH CO LTD·Filed 2016·Granted Apr 7, 2020·4 cites·20 claims
- 1281US9583390B2Organic thin film passivation of metal interconnectionsINTEL CORP·Filed 2016·Granted Feb 28, 2017·3 cites·12 claims
- 1381US9257276B2Organic thin film passivation of metal interconnectionsALEKSOV ALEKSANDAR·Filed 2011·Granted Feb 9, 2016·5 cites·27 claims
- 1477US6888246B2Semiconductor power device with shear stress compensationFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted May 3, 2005·22 cites·9 claims
- 1575US7545030B2Article having metal impregnated within carbon nanotube arrayINTEL CORP·Filed 2005·Granted Jun 9, 2009·10 cites·26 claims
- 1673US9859248B2Laser die backside film removal for integrated circuit (IC) packagingINTEL CORP·Filed 2016·Granted Jan 2, 2018·2 cites·20 claims
- 1771US7971347B2Method of interconnecting workpiecesINTEL CORP·Filed 2008·Granted Jul 5, 2011·7 cites·6 claims
- 1868US9824991B2Organic thin film passivation of metal interconnectionsINTEL CORP·Filed 2017·Granted Nov 21, 2017·1 cites·20 claims
- 1968US8072062B2Circuit device with at least partial packaging and method for formingLEAL GEORGE R·Filed 2008·Granted Dec 6, 2011·3 cites·14 claims
- 2067US9412702B2Laser die backside film removal for integrated circuit (IC) packagingINTEL CORP·Filed 2013·Granted Aug 9, 2016·2 cites·12 claims
- 2162US9613933B2Package structure to enhance yield of TMI interconnectionsDE BONIS THOMAS J·Filed 2014·Granted Apr 4, 2017·2 cites·20 claims
- 2261US8404519B2Process that includes assembling together first and second substrates the have respective first and second carbon nanotube arrays with geometrically complementary patternsCHRYSLER GREGORY M·Filed 2011·Granted Mar 26, 2013·2 cites·8 claims
- 2357US7964447B2Process of making carbon nanotube array that includes impregnating the carbon nanotube array with metalINTEL CORP·Filed 2009·Granted Jun 21, 2011·3 cites·8 claims
- 2455US10128225B2Interconnect structures with polymer coreINTEL CORP·Filed 2017·Granted Nov 13, 2018·0 cites·7 claims
- 2555US8674519B2Microelectronic package and method of manufacturing sameARANA LEONEL R·Filed 2010·Granted Mar 18, 2014·1 cites·15 claims
- 2652US10049971B2Package structure to enhance yield of TMI interconnectionsINTEL CORP·Filed 2017·Granted Aug 14, 2018·0 cites·3 claims
- 2752US9165914B2Forming die backside coating structures with coreless packagesINTEL CORP·Filed 2013·Granted Oct 20, 2015·0 cites·12 claims
- 2852US6664200B1Method of manufacturing a semiconductor component and polyimide etchant thereforMOTOROLA INC·Filed 2000·Granted Dec 16, 2003·3 cites·30 claims
- 2951US9613934B2Interconnect structures with polymer coreINTEL CORP·Filed 2015·Granted Apr 4, 2017·0 cites·10 claims
- 3050US2008305603A1Forming carbon nanotube capacitorsMOSLEY LARRY E·Filed 2008·Application pending·0 cites
- 3148US9472517B2Dry-removable protective coatingsOKA MIHIR A·Filed 2014·Granted Oct 18, 2016·0 cites·16 claims
- 3247US10867959B2Integrated circuit packaging method and integrated packaged circuitSHENZHEN XIUYUAN ELECTRONIC TECH CO LTD·Filed 2016·Granted Dec 15, 2020·0 cites·15 claims
- 3347US2017033069A1Dry-removable protective coatingsINTEL CORP·Filed 2016·Application pending·0 cites
- 3445US10573622B2Methods of forming joint structures for surface mount packagesINTEL CORP·Filed 2017·Granted Feb 25, 2020·0 cites·8 claims
- 3545US2007000595A1Adhesive substrate and method for usingINTEL CORP·Filed 2005·Application pending·0 cites
- 3644US9659889B2Solder-on-die using water-soluble resist system and methodINTEL CORP·Filed 2013·Granted May 23, 2017·0 cites·6 claims
- 3744US2009294515A1Mounting integrated circuit components on substratesPRACK EDWARD R·Filed 2008·Application pending·0 cites
- 3841US2006286768A1Method of supporting microelectronic wafer during backside processingINTEL CORP·Filed 2005·Application pending·0 cites
- 3939US2006273454A1Locking mechanism for die assemblyLU DAOGIANG·Filed 2005·Application pending·0 cites
- 4038US11183458B2Integrated circuit packaging structure and methodSHENZHEN XIUYUAN ELECTRONIC TECH CO LTD·Filed 2016·Granted Nov 23, 2021·0 cites·7 claims
- 4136US10930634B2Integrated circuit system and packaging method thereforSHENZHEN XIUYUAN ELECTRONIC TECH CO LTD·Filed 2016·Granted Feb 23, 2021·0 cites·19 claims
- 4235US11335664B2Integrated circuit packaging method and integrated packaging circuitSHENZHEN XIUYUAN ELECTRONIC TECH CO LTD·Filed 2016·Granted May 17, 2022·0 cites·13 claims
- 4335US9786517B2Ablation method and recipe for wafer level underfill material patterning and removalDIAS RAJENDRA C·Filed 2013·Granted Oct 10, 2017·0 cites·13 claims
- 4432US2007004171A1Method of supporting microelectronic wafer during backside processing using carrier having radiation absorbing film thereonARANA LEONEL R·Filed 2005·Application pending·0 cites
- 4531US2015072515A1Laser ablation method and recipe for sacrificial material patterning and removalDIAS RAJENDRA C·Filed 2013·Application pending·0 cites
- 4628US11710646B2Fan-out packaging method and fan-out packaging plateSHENZHEN XIUYI INVESTMENT DEVELOPMENT PARTNERSHIP LP·Filed 2018·Granted Jul 25, 2023·0 cites·15 claims
Join the waitlist — get patent alerts
Get an alert when Edward R. Prack files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →