Inventor · disambiguated record
Tobias Werner
Also filed as: WERNER TOBIAS · WERNER TOBIAS T
36 granted patents·7 pending applications·65 citations·filing 2004–2023
95Inventor score
Top patents by PatentIndex Score
43 records- 0193US9406375B1Write address synchronization in 2 read/1write SRAM arraysIBM·Filed 2015·Granted Aug 2, 2016·16 cites·12 claims
- 0280US10833089B2Buried conductive layer supplying digital circuitsIBM·Filed 2018·Granted Nov 10, 2020·3 cites·18 claims
- 0380US7557614B1Topology for a n-way XOR/XNOR circuitIBM·Filed 2008·Granted Jul 7, 2009·12 cites·1 claims
- 0475US11164879B2Microelectronic device with a memory element utilizing stacked vertical devicesIBM·Filed 2018·Granted Nov 2, 2021·2 cites·23 claims
- 0572US8918749B2Integrated circuit schematics having imbedded scaling information for generating a design instanceIBM·Filed 2013·Granted Dec 23, 2014·3 cites·6 claims
- 0672US7936638B2Enhanced programmable pulsewidth modulating circuit for array clock generationIBM·Filed 2009·Granted May 3, 2011·6 cites·19 claims
- 0768US9236826B2Control device and method for operating an electrical machine driven by an inverterDJONGA CHRISTIAN·Filed 2012·Granted Jan 12, 2016·5 cites·10 claims
- 0866US9437285B1Write address synchronization in 2 read/1write SRAM arraysIBM·Filed 2016·Granted Sep 6, 2016·2 cites·8 claims
- 0962US9401698B1Transforming a phase-locked-loop generated chip clock signal to a local clock signalIBM·Filed 2015·Granted Jul 26, 2016·1 cites·17 claims
- 1061US9401597B2Method and device for discharging an intermediate circuit of a power supply networkBOSCH GMBH ROBERT·Filed 2013·Granted Jul 26, 2016·2 cites·13 claims
- 1159US7546565B2Method for comparing two designs of electronic circuitsIBM·Filed 2007·Granted Jun 9, 2009·2 cites·6 claims
- 1258US9792967B1Managing semiconductor memory array leakage currentIBM·Filed 2016·Granted Oct 17, 2017·1 cites·14 claims
- 1358US8587990B2Global bit line restore by most significant bit of an address lineCHAN YUEN H·Filed 2011·Granted Nov 19, 2013·2 cites·15 claims
- 1458US7401312B2Automatic method for routing and designing an LSIIBM·Filed 2004·Granted Jul 15, 2008·5 cites·7 claims
- 1557US9786339B2Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservationIBM·Filed 2016·Granted Oct 10, 2017·1 cites·18 claims
- 1654US2025013811A1Modifying netlists for device changes in ic designsIBM·Filed 2023·Application pending·0 cites
- 1752US10565340B2Field-effect transistor placement optimization for improved leaf cell routabilityIBM·Filed 2017·Granted Feb 18, 2020·0 cites·3 claims
- 1852US8964493B2Defective memory column replacement with load isolationIBM·Filed 2013·Granted Feb 24, 2015·1 cites·20 claims
- 1951US11328110B2Integrated circuit including logic circuitryIBM·Filed 2020·Granted May 10, 2022·0 cites·15 claims
- 2051US8631376B2Method and system for generating a placement layout of a VLSI circuit designWERNER TOBIAS·Filed 2012·Granted Jan 14, 2014·1 cites·14 claims
- 2151US2008301616A1Layout Generator for Routing and Designing an LSIIBM·Filed 2008·Application pending·0 cites
- 2250US10394994B2Field-effect transistor placement optimization for improved leaf cell routabilityIBM·Filed 2017·Granted Aug 27, 2019·0 cites·7 claims
- 2349US10804266B2Microelectronic device utilizing stacked vertical devicesIBM·Filed 2018·Granted Oct 13, 2020·0 cites·24 claims
- 2449US9904754B2Layout of interconnect lines in integrated circuitsIBM·Filed 2016·Granted Feb 27, 2018·0 cites·12 claims
- 2547US9898571B2Layout of interconnect lines in integrated circuitsIBM·Filed 2016·Granted Feb 20, 2018·0 cites·20 claims
- 2646US10712568B2Projection device for data eyeglasses, data eyeglasses, and method for operating a projection device for data eyeglassesBOSCH GMBH ROBERT·Filed 2016·Granted Jul 14, 2020·0 cites·16 claims
- 2745US9837142B1Automated stressing and testing of semiconductor memory cellsIBM·Filed 2016·Granted Dec 5, 2017·0 cites·9 claims
- 2845US9805823B1Automated stressing and testing of semiconductor memory cellsIBM·Filed 2017·Granted Oct 31, 2017·0 cites·8 claims
- 2945US9627090B1RAM at speed flexible timing and setup controlIBM·Filed 2015·Granted Apr 18, 2017·0 cites·8 claims
- 3045US2025077759A1Layout and schematic inconsistency checking across hierarchical boundaries and preventative design conventionsIBM·Filed 2023·Application pending·0 cites
- 3144US9997218B2Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservationIBM·Filed 2017·Granted Jun 12, 2018·0 cites·1 claims
- 3243US9761289B1Managing semiconductor memory array leakage currentIBM·Filed 2016·Granted Sep 12, 2017·0 cites·6 claims
- 3343US9537474B2Transforming a phase-locked-loop generated chip clock signal to a local clock signalIBM·Filed 2015·Granted Jan 3, 2017·0 cites·8 claims
- 3441US9627017B1RAM at speed flexible timing and setup controlIBM·Filed 2015·Granted Apr 18, 2017·0 cites·12 claims
- 3540US11467078B2Laser-induced incandescent particle sensor comprising a confocal arrangement of a laser spot and of a thermal radiation spotBOSCH GMBH ROBERT·Filed 2019·Granted Oct 11, 2022·0 cites·15 claims
- 3640US11171142B2Integrated circuit with vertical structures on nodes of a gridIBM·Filed 2018·Granted Nov 9, 2021·0 cites·24 claims
- 3738US9711244B1Memory circuitIBM·Filed 2016·Granted Jul 18, 2017·0 cites·16 claims
- 3838US9384823B2SRAM array comprising multiple cell coresIBM·Filed 2014·Granted Jul 5, 2016·0 cites·18 claims
- 3936US8837235B1Local evaluation circuit for static random-access memoryIBM·Filed 2013·Granted Sep 16, 2014·0 cites·20 claims
- 4036US2012005643A1System and Method for Placing Integrated Circuit Functional Blocks According to Dataflow WidthSCHROEDER FRIEDRICH·Filed 2010·Application pending·0 cites
- 4135US2008258769A1Tri-State Circuit Element Plus Tri-State-Multiplexer CircuitryIBM·Filed 2008·Application pending·0 cites
- 4232US2011317478A1Method and Circuit Arrangement for Performing a Write Through Operation, and SRAM Array With Write Through CapabilityCHAN YUEN H·Filed 2011·Application pending·0 cites
- 4331US2011310680A1Interleave Memory Array ArrangementCHAN YUEN H·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →