Inventor · disambiguated record
Daniel Leibholz
Also filed as: LEIBHOLZ DANIEL · LEIBHOLZ DANIEL L · LEIBHOLZ DANIEL LAWRENCE
18 granted patents·5 pending applications·920 citations·filing 1990–2004
96Inventor score
Technology areasG06F
Files withSUN MICROSYSTEMS INC6COMPAQ COMPUTER CORP5HEWLETT PACKARD DEVELOPMENT CO4COMPAQ INFORMATION TECHNOLOGIE2DIGITAL EQUIPMENT CORP2
Top patents by PatentIndex Score
23 records- 0194US6954846B2Microprocessor and method for giving each thread exclusive access to one register file in a multi-threading mode and for giving an active thread access to multiple register files in a single thread modeSUN MICROSYSTEMS INC·Filed 2001·Granted Oct 11, 2005·119 cites·19 claims
- 0291US7418582B1Versatile register file design for a multi-threaded processor utilizing different modes and register windowsSUN MICROSYSTEMS INC·Filed 2004·Granted Aug 26, 2008·70 cites·24 claims
- 0390US6000044AApparatus for randomly sampling instructions in a processor pipelineDIGITAL EQUIPMENT CORP·Filed 1997·Granted Dec 7, 1999·169 cites·29 claims
- 0481US6195748B1Apparatus for sampling instruction execution information in a processor pipelineCOMPAQ COMPUTER CORP·Filed 1997·Granted Feb 27, 2001·96 cites·49 claims
- 0579US6163840AMethod and apparatus for sampling multiple potentially concurrent instructions in a processor pipelineCOMPAQ COMPUTER CORP·Filed 1997·Granted Dec 19, 2000·87 cites·39 claims
- 0679US5103393AMethod of dynamically allocating processors in a massively parallel processing systemDIGITAL EQUIPMENT CORP·Filed 1990·Granted Apr 7, 1992·107 cites·16 claims
- 0775US6098166ASpeculative issue of instructions under a load miss shadowCOMPAQ COMPUTER CORP·Filed 1998·Granted Aug 1, 2000·73 cites·18 claims
- 0871US6675288B2Apparatus for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register listHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Jan 6, 2004·16 cites·16 claims
- 0967US6141734AMethod and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocolCOMPAQ COMPUTER CORP·Filed 1998·Granted Oct 31, 2000·51 cites·15 claims
- 1064US6662293B1Instruction dependency scoreboard with a hierarchical structureSUN MICROSYSTEMS INC·Filed 2000·Granted Dec 9, 2003·11 cites·20 claims
- 1162US6542987B1Method and circuits for early detection of a full queueHEWLETT PACKARD DEVELOPMENT CO·Filed 1999·Granted Apr 1, 2003·31 cites·43 claims
- 1260US7493615B2Apparatus and method for synchronizing multiple threads in an out-of-order microprocessorSUN MICROSYSTEMS INC·Filed 2003·Granted Feb 17, 2009·12 cites·7 claims
- 1349US6449713B1Implementation of a conditional move instruction in an out-of-order processorCOMPAQ INFORMATION TECHNOLOGIE·Filed 1998·Granted Sep 10, 2002·20 cites·23 claims
- 1448US2005038979A1Method and circuits for early detection of a full queueFiled 2004·Application pending·0 cites
- 1548US2004220794A1Methods and apparatus for generating effective test code for out of order superscalar microprocessorsFiled 2004·Application pending·0 cites
- 1647US8090930B2Method and circuits for early detection of a full queueFISCHER TIMOTHY CHARLES·Filed 2003·Granted Jan 3, 2012·2 cites·21 claims
- 1746US2004098566A1Method and apparatus for compacting a queueFiled 2003·Application pending·0 cites
- 1845US6122728ATechnique for ordering internal processor register accessesCOMPAQ COMPUTER CORP·Filed 1998·Granted Sep 19, 2000·19 cites·21 claims
- 1943US6704856B1Method for compacting an instruction queueHEWLETT PACKARD DEVELOPMENT CO·Filed 1999·Granted Mar 9, 2004·14 cites·2 claims
- 2041US6813702B1Methods and apparatus for generating effective test code for out of order super scalar microprocessorsHEWLETT PACKARD DEVELOPMENT CO·Filed 1998·Granted Nov 2, 2004·11 cites·18 claims
- 2140US6405304B1Method for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register listCOMPAQ INFORMATION TECHNOLOGIE·Filed 1998·Granted Jun 11, 2002·12 cites·8 claims
- 2240US2002138714A1Scoreboard for scheduling of instructions in a microprocessor that provides out of order executionSUN MICROSYSTEMS INC·Filed 2001·Application pending·0 cites
- 2337US2002083309A1Hardware spill/fill engine for register windowsSUN MICROSYSTEMS INC·Filed 2000·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →