Methods and apparatus for generating effective test code for out of order superscalar microprocessors

Abstract

A technique for producing a test executable in a computer. The technique involves forming multiple instruction streams. The technique further involves dividing the multiple instruction streams into portions, and generating a combined instruction stream having the portions interleaved. Additionally, the technique involves creating a test executable from the combined instruction stream. The test executable can be used for testing a simulated processor in a computer. In particular, the test executable is loaded. Then, the test executable is run through the simulated processor to generate processor results and through a reference model to generate reference results. The processor results and the reference results are compared to determine whether the simulated processor operates correctly.

What is claimed is:  
     
         1 . A method for testing a simulated processor in a computer, comprising the steps of: 
 loading a test executable created from a combined instruction stream having interleaved portions of multiple instruction streams;    running the loaded test executable through the simulated processor to generate processor results and through a reference model to generate reference results; and comparing the processor results and the reference results to determine whether the simulated processor operates correctly.    
     
     
         2 . The method of  claim 1 , wherein the multiple instruction streams access different groups of registers, and wherein the step of running includes the step of: 
 executing the test executable such that each of the different groups of registers is accessed.    
     
     
         3 . A simulation system for testing a simulated processor, comprising: 
 an input that receives a test executable created from a combined instruction stream having interleaved portions of multiple instruction streams;    a processor simulator, coupled to the input, that runs the test executable to generate processor results;    a reference model, coupled to the input, that runs the test executable to generate reference results; and    a compare module, coupled to the processor simulator and the reference model, that compares the processor results and the reference results to determine whether the simulated processor operates correctly.    
     
     
         4 . The simulation system of  claim 3 , wherein the multiple instruction streams access different groups of registers, and wherein the processor simulator includes: 
 registers that are accessed in the different groups when the processor simulator runs the test executable.