Inventor · disambiguated record
Ruban Kanapathipillai
Also filed as: KANAPATHIPILLAI RUBAN · KANAPATHIPPILLAI RUBAN
15 granted patents·3 pending applications·304 citations·filing 1999–2005
94Inventor score
Technology areasG06F
Top patents by PatentIndex Score
18 records- 0193US6842850B2DSP data type matching for operation using multiple functional unitsINTEL CORP·Filed 2003·Granted Jan 11, 2005·74 cites·15 claims
- 0284US6832306B1Method and apparatus for a unified RISC/DSP pipeline controller for both reduced instruction set computer (RISC) control instructions and digital signal processing (DSP) instructionsINTEL CORP·Filed 2000·Granted Dec 14, 2004·41 cites·39 claims
- 0384US6598155B1Method and apparatus for loop buffering digital signal processing instructionsINTEL CORP·Filed 2000·Granted Jul 22, 2003·37 cites·14 claims
- 0484US6446195B1Dyadic operations instruction processor with configurable functional blocksINTEL CORP·Filed 2000·Granted Sep 3, 2002·25 cites·35 claims
- 0582US6557096B1Processors with data typer and aligner selectively coupling data bits of data buses to adder and multiplier functional blocks to execute instructions with flexible data typesINTEL CORP·Filed 2000·Granted Apr 29, 2003·27 cites·33 claims
- 0678US7062637B2DSP operations with permutation of vector complex data type operandsINTEL CORP·Filed 2003·Granted Jun 13, 2006·20 cites·26 claims
- 0777US6842845B2Methods and apparatuses for signal processingINTEL CORP·Filed 2001·Granted Jan 11, 2005·21 cites·13 claims
- 0869US6643768B2Dyadic DSP instruction processor with main and sub-operation functional blocks selected from each set of multiplier and adderINTEL CORP·Filed 2002·Granted Nov 4, 2003·8 cites·41 claims
- 0966US6631461B2Dyadic DSP instructions for digital signal processorsINTEL CORP·Filed 2002·Granted Oct 7, 2003·6 cites·24 claims
- 1066US6408376B1Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneouslyINTEL CORP·Filed 2000·Granted Jun 18, 2002·10 cites·33 claims
- 1159US6988184B2Dyadic DSP instruction predecode signal selective multiplexing data from input buses to first and second plurality of functional blocks to execute main and sub operationsINTEL CORP·Filed 2002·Granted Jan 17, 2006·3 cites·13 claims
- 1258US6766446B2Method and apparatus for loop buffering digital signal processing instructionsINTEL CORP·Filed 2003·Granted Jul 20, 2004·5 cites·15 claims
- 1356US6772319B2Dyadic instruction processing instruction set architecture with 20-bit and 40-bit DSP and control instructionsINTEL CORP·Filed 2002·Granted Aug 3, 2004·2 cites·10 claims
- 1454US6748516B2Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneouslyINTEL CORP·Filed 2002·Granted Jun 8, 2004·3 cites·19 claims
- 1551US2006112260A1Method and apparatus of instruction execution for signal processorsGANAPATHY KUMAR·Filed 2005·Application pending·0 cites
- 1651US2006112259A1Method and apparatus for instruction set architecture with control instructions for signal processorsGANAPATHY KUMAR·Filed 2005·Application pending·0 cites
- 1749US6330660B1Method and apparatus for saturated multiplication and accumulation in an application specific signal processorVXTEL INC·Filed 1999·Granted Dec 11, 2001·22 cites·17 claims
- 1847US2004093481A1Method and apparatus for instruction set architecture having dyadic digital signal processing instructionsFiled 2003·Application pending·0 cites
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