Method and apparatus of instruction execution for signal processors

Abstract

An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The instruction set architecture implemented with the ASSP, is adapted to DSP algorithmic structures. The instruction word of the ISA is typically 20 bits but can be expanded to 40-bits to control two instructions to be executed in series or parallel. All DSP instructions of the ISA are dyadic DSP instructions performing two operations with one instruction in one cycle. The DSP instructions or operations in the preferred embodiment include a multiply instruction (MULT), an addition instruction (ADD), a minimize/maximize instruction (MIN/MAX) also referred to as an extrema instruction, and a no operation instruction (NOP) each having an associated operation code (“opcode”). The present invention efficiently executes DSP instructions by means of the instruction set architecture and the hardware architecture of the application specific signal processor.

1 - 20 . (canceled)  
   
   
       21 . A method of instruction execution for a signal processor, the method comprising: 
 writing a dyadic DSP instruction having a main operation and a sub operation into a memory;    reading the dyadic DSP instruction from the memory to begin execution of the main operation and the sub operation; and    addressing at least three operands for execution with the main operation and the sub operation.    
   
   
       22 . The method of  claim 21 , further comprising: 
 executing the main operation and the sub operation using the at least three operands.    
   
   
       23 . The method of  claim 22 , further comprising: 
 storing the results of the execution of the dyadic DSP instruction.    
   
   
       24 . The method of  claim 21 , wherein, 
 the addressing addresses a register for one source of one of the at least three operands.    
   
   
       25 . The method of  claim 21 , wherein, 
 the addressing addresses a register that contains a pointer to an address into the memory for one source of one of the at least three operands.    
   
   
       26 . The method of  claim 21 , wherein, 
 the addressing addresses the memory for one source of one of the at least three operands.    
   
   
       27 . The method of  claim 21 , wherein, 
 the main operation and the sub operation are two operations selected from the set of multiplication, addition, comparison with a minimum or maximum value, and no operation.    
   
   
       28 . A method in a signal processor, the method comprising: in response to a dyadic DSP instruction, 
 selecting input and output data paths between a plurality of DSP functional blocks;    executing a main operation of the dyadic DSP instruction on a first pair of operands using the plurality of DSP functional blocks;    executing a sub operation of the dyadic DSP instruction on a second pair of operands using the plurality of DSP functional blocks; and    storing the results of the execution of the main operation and the sub operation of the dyadic DSP instruction.    
   
   
       29 . The method of  claim 28 , further comprising: 
 prior to the executing, addressing at least three operands for execution with the main operation and the sub operation.    
   
   
       30 . The method of  claim 29 , wherein, 
 one of the at least three operands for execution is a result of the execution of the main operation or the sub operation.    
   
   
       31 . The method of  claim 28 , wherein, 
 the execution of the main operation and the sub operation are performed in parallel during the same cycle.    
   
   
       32 . The method of  claim 28 , wherein, 
 the execution of the main operation and the sub operation are performed sequentially during different cycles.    
   
   
       33 . The method of  claim 28 , wherein, 
 the main operation and the sub operation are two operations selected from the set of multiplication, addition, comparison with a minimum or maximum value, and no operation.