Method and apparatus for instruction set architecture with control instructions for signal processors

Abstract

An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The instruction set architecture implemented with the ASSP, is adapted to DSP algorithmic structures. The instruction word of the ISA is typically 20 bits but can be expanded to 40-bits to control two instructions to be executed in series or parallel. All DSP instructions of the ISA are dyadic DSP instructions performing two operations with one instruction in one cycle. The DSP instructions or operations in the preferred embodiment include a multiply instruction (MULT), an addition instruction (ADD), a minimize/maximize instruction (MIN/MAX) also referred to as an extrema instruction, and a no operation instruction (NOP) each having an associated operation code (“opcode”). The present invention efficiently executes DSP instructions by means of the instruction set architecture and the hardware architecture of the application specific signal processor.

1 - 13 . (canceled)  
   
   
       14 . An instruction set architecture (ISA) for execution of operations within a digital signal processor, the instruction set architecture comprising: 
 a set of instructions for operation within a digital signal processor wherein each instruction includes a first operand accessed directly from memory, a second operand accessed directly from memory of a local register, and a destination register to store results, the set of instructions including, 
 a 20-bit DSP instruction, and  
 a 40-bit DSP instruction,  
 the set of instructions to accelerate calculations within the digital signal processor of the type where D=[(A operation one B) operation two C] where operation one and operation two are separate signal processing operations.  
   
   
   
       15 . The instruction set architecture (ISA) of  claim 14  for execution of operations within a digital signal processor, wherein, 
 the twenty bit instruction uses mode bits in control registers and the forty bit instruction has a control extension to override the mode bits.    
   
   
       16 . The instruction set architecture (ISA) of  claim 14  for execution of operations within a digital signal processor, wherein, 
 the set of instructions further includes a dyadic instruction to execute two operations in one instruction.    
   
   
       17 . The instruction set architecture (ISA) of  claim 16  for execution of operations within a digital signal processor, wherein 
 the two operations of the dyadic instruction for execution in one instruction are DSP operations.    
   
   
       18 . The instruction set architecture (ISA) of  claim 17  for execution of operations within a digital signal processor, wherein 
 the DSP operations are of the set of operations of multiplication, addition, extremum, and no operation.    
   
   
       19 - 20 . (canceled)  
   
   
       21 . The instruction set architecture (ISA) of  claim 15  for execution of operations within a digital signal processor, wherein, 
 the control registers are mode registers.    
   
   
       22 . An instruction set architecture to perform digital signal processing functions for the communication of voice and data over a communication system the instruction set architecture comprising: 
 a plurality of digital signal processing (DSP) instructions for performing DSP operations within a processor, the plurality of DSP instructions accessing at least a first operand and a second operand to perform the instruction and writing a result upon completion, the plurality of DSP instructions to perform DSP operations within a plurality of core digital signal processors of the processor; and    a plurality of control instructions for controlling the execution of the plurality of DSP instructions, the plurality of control instructions executed by a RISC processor of the processor to control the DSP operations within the plurality of core digital signal processors.    
   
   
       23 . The instruction set architecture of  claim 22 , wherein 
 at least one of the plurality of DSP instructions is a dyadic DSP instruction including a main digital signal processing operation and a sub digital signal processing operation.    
   
   
       24 . The instruction set architecture of  claim 22 , wherein, 
 the plurality of DSP instructions include bits to access operands in memory and registers.    
   
   
       25 . The instruction set architecture of  claim 22 , wherein, 
 the plurality of DSP instructions and the plurality of control instructions include bits to perform execution prediction of branches and jumps of a program.    
   
   
       26 . The instruction set architecture of  claim 22 , wherein 
 the digital signal processing operations are of the set of operations of multiplication, addition, extremum, and no operation.    
   
   
       27 . The instruction set architecture of  claim 22 , wherein 
 the plurality of DSP instructions to accelerate calculations within the digital signal processor of the type where D=[(A operation one B) operation two C] where operation one and operation two are separate signal processing operations.    
   
   
       28 . An instruction set architecture to convert voice and data samples into packets for transmission over a network and to convert packets received from the network into voice and data samples, the instruction set architecture comprising: 
 a plurality of digital signal processing (DSP) instructions for performing DSP operations within a processor, the plurality of DSP instructions accessing at least a first operand and a second operand to perform the instruction and writing a result upon completion, the plurality of DSP instructions to perform DSP operations within a plurality of core digital signal processors, the plurality of DSP instructions including, 
 a 20-bit DSP instruction, and  
 a 40-bit DSP instruction; and  
   a plurality of control instructions for controlling the execution of the plurality of DSP instructions, the plurality of control instructions executed by a RISC processor to control the DSP operations within the plurality of core digital signal processors, the plurality of control instructions including, 
 a 20-bit control instruction, and  
 a 40-bit control instruction.  
   
   
   
       29 . The instruction set architecture of  claim 28 , wherein, 
 the 40-bit DSP instruction and the 20-bit control instruction include bits to perform execution prediction of branches and jumps of a program.    
   
   
       30 . The instruction set architecture of  claim 28 , wherein, 
 the execution prediction depends upon a condition to change instruction execution.    
   
   
       31 . The instruction set architecture of  claim 30 , wherein, 
 the 40-bit DSP instruction include bits to access operands in memory and registers.