Inventor · disambiguated record
Larisa Novakovsky
Also filed as: NOVAKOVSKY LARISA
25 granted patents·8 pending applications·58 citations·filing 2005–2023
94Inventor score
Top patents by PatentIndex Score
33 records- 0195US11048512B1Apparatus and method to identify the source of an interruptINTEL CORP·Filed 2020·Granted Jun 29, 2021·4 cites·24 claims
- 0289US9710041B2Masking a power state of a core of a processorINTEL CORP·Filed 2015·Granted Jul 18, 2017·7 cites·21 claims
- 0385US10725848B2Supporting hang detection and data recovery in microprocessor systemsINTEL CORP·Filed 2018·Granted Jul 28, 2020·5 cites·20 claims
- 0482US9471494B2Method and apparatus for cache line write back operationINTEL CORP·Filed 2013·Granted Oct 18, 2016·7 cites·21 claims
- 0579US9830272B2Cache memory staged reopenSORANI IRIS·Filed 2011·Granted Nov 28, 2017·7 cites·26 claims
- 0675US11900115B2Apparatus and method to identify the source of an interruptINTEL CORP·Filed 2023·Granted Feb 13, 2024·0 cites·7 claims
- 0775US9990287B2Apparatus and method for memory-hierarchy aware producer-consumer instructionRAIKIN SHLOMO·Filed 2011·Granted Jun 5, 2018·4 cites·21 claims
- 0875US9448879B2Apparatus and method for implement a multi-level memory hierarchyYIGZAW THEODROS·Filed 2011·Granted Sep 20, 2016·4 cites·24 claims
- 0975US9367464B2Cache circuit having a tag array with smaller latency than a data arrayNOVAKOVSKY LARISA·Filed 2011·Granted Jun 14, 2016·5 cites·19 claims
- 1070US10775434B2System, apparatus and method for probeless field scan of a processorINTEL CORP·Filed 2018·Granted Sep 15, 2020·1 cites·20 claims
- 1170US9378148B2Adaptive hierarchical cache policy in a microprocessorINTEL CORP·Filed 2013·Granted Jun 28, 2016·2 cites·26 claims
- 1269US11614939B2Apparatus and method to identify the source of an interruptINTEL CORP·Filed 2021·Granted Mar 28, 2023·0 cites·22 claims
- 1369US8990512B2Method and apparatus for error correction in a cacheINTEL CORP·Filed 2012·Granted Mar 24, 2015·2 cites·24 claims
- 1467US8347035B2Posting weakly ordered transactionsINTEL CORP·Filed 2008·Granted Jan 1, 2013·4 cites·20 claims
- 1566US9360924B2Reduced power mode of a cache unitINTEL CORP·Filed 2013·Granted Jun 7, 2016·2 cites·20 claims
- 1664US10157136B2Pipelined prefetcher for parallel advancement of multiple data streamsINTEL CORP·Filed 2016·Granted Dec 18, 2018·1 cites·20 claims
- 1761US7958510B2Device, system and method of managing a resource requestINTEL CORP·Filed 2005·Granted Jun 7, 2011·2 cites·20 claims
- 1857US8996833B2Multi latency configurable cacheNOVAKOVSKY LARISA·Filed 2013·Granted Mar 31, 2015·1 cites·25 claims
- 1956US10719326B2Communicating via a mailbox interface of a processorINTEL CORP·Filed 2018·Granted Jul 21, 2020·0 cites·20 claims
- 2052US9684595B2Adaptive hierarchical cache policy in a microprocessorINTEL CORP·Filed 2016·Granted Jun 20, 2017·0 cites·19 claims
- 2150US9535476B2Apparatus and method to transfer data packets between domains of a processorINTEL CORP·Filed 2014·Granted Jan 3, 2017·0 cites·20 claims
- 2249US2020349312A1Core-Only System Management InterruptINTEL CORP·Filed 2020·Application pending·0 cites
- 2348US10990534B2Device, system and method to facilitate disaster recovery for a multi-processor platformINTEL CORP·Filed 2019·Granted Apr 27, 2021·0 cites·22 claims
- 2447US10628542B2Core-only system management interruptINTEL CORP·Filed 2017·Granted Apr 21, 2020·0 cites·22 claims
- 2545US10175992B2Systems and methods for enhancing BIOS performance by alleviating code-size limitationsINTEL CORP·Filed 2016·Granted Jan 8, 2019·0 cites·20 claims
- 2645US9471088B2Restricting clock signal delivery in a processorINTEL CORP·Filed 2013·Granted Oct 18, 2016·0 cites·16 claims
- 2745US2016224098A1Communicating via a mailbox interface of a processorGENDLER ALEXANDER·Filed 2015·Application pending·0 cites
- 2843US2023325241A1Hardware and configuration support for allocating shared resourcesINTEL CORP·Filed 2020·Application pending·0 cites
- 2943US2023315630A1Dynamic inclusive and non-inclusive caching policyINTEL CORP·Filed 2022·Application pending·0 cites
- 3042US2014208031A1Apparatus and method for memory-hierarchy aware producer-consumer instructionsRAIKIN SHLOMO·Filed 2011·Application pending·0 cites
- 3142US2019102324A1Cache behavior for secure memory repartitioning systemsINTEL CORP·Filed 2017·Application pending·0 cites
- 3235US2013262826A1Apparatus and method for dynamically managing memory access bandwidth in multi-core processorGENDLER ALEXANDER·Filed 2011·Application pending·0 cites
- 3335US2016283232A1Instruction and Logic for Speculative Request Support for PrefetchingSADE RAANAN·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →