Core-Only System Management Interrupt

Abstract

An apparatus, including: a deterministic monitored device; an interconnect to communicatively couple the monitored device to a support circuit; a super queue to queue transactions between the monitored device and the support circuit, the super queue including an operational segment and a shadow segment; a debug data structure; and a system management agent to monitor transactions in the operational segment, log corresponding transaction identifiers in the shadow segment, and write debug data to the debug data structure, wherein the debug data are at least partly based on the corresponding transaction identifiers.

1 .- 24 . (canceled) 
     
     
         25 . An apparatus, comprising:
 a deterministic device;   support circuitry coupled to the deterministic device via an interface;   wherein the deterministic device comprises a super queue to log outbound transactions from the deterministic device to the support circuitry and log inbound transactions from the support circuitry to the deterministic core corresponding to the outbound transactions; and   wherein the support circuitry comprises a system management agent to write debug data to a debug data structure based on the logged inbound transactions in the super queue.   
     
     
         26 . The apparatus of  claim 25 , wherein the support circuitry is non-deterministic. 
     
     
         27 . The apparatus of  claim 25 , wherein the super queue comprises an operational segment to log the outbound transactions, and a shadow segment to log the inbound transactions. 
     
     
         28 . The apparatus of  claim 27 , wherein the operational segment and shadow segment are equal in size. 
     
     
         29 . The apparatus of  claim 27 , wherein the super queue is to store read operations as outbound transactions in the operational segment, and inbound write operations corresponding to the read operations in the shadow segment. 
     
     
         30 . The apparatus of  claim 29 , wherein the super queue to log, in the shadow segment, a time stamp for the inbound write and a result code. 
     
     
         31 . The apparatus of  claim 30 , wherein the super queue is further to log, in the shadow segment, the inbound data associated with the inbound write. 
     
     
         32 . The apparatus of  claim 25 , further comprising circuitry coupled to the interface to capture one or more of asynchronous transactions and snoops. 
     
     
         33 . The apparatus of  claim 25 , wherein the deterministic device is a processor core. 
     
     
         34 . The apparatus of  claim 33 , wherein the support circuitry is an uncore circuit. 
     
     
         35 . The apparatus of  claim 33 , wherein the support circuitry is an intellectual property (IP) block. 
     
     
         36 . The apparatus of  claim 25 , wherein the deterministic device is a graphics processor. 
     
     
         37 . The apparatus of  claim 25 , wherein the apparatus is a system-on-chip (SoC). 
     
     
         38 . A system, comprising:
 a deterministic core;   non-deterministic support circuitry;   an interface to communicatively couple the core to the support circuitry; and   an emulation store;   wherein the deterministic device comprises a super queue to log outbound transactions from the deterministic device to the non-deterministic support circuitry and log inbound transactions from the non-deterministic support circuitry to the deterministic core corresponding to the outbound transactions; and   wherein the non-deterministic support circuitry comprises a system management agent to write debug data to a debug data structure based on the logged inbound transactions in the super queue.   
     
     
         39 . The system of  claim 38 , wherein the super queue comprises an operational segment to log the outbound transactions, and a shadow segment to log the inbound transactions. 
     
     
         40 . The system of  claim 39 , wherein the operational segment and shadow segment are equal in size. 
     
     
         41 . The system of  claim 39 , wherein the super queue is to store read operations as outbound transactions in the operational segment, and inbound write operations corresponding to the read operations in the shadow segment. 
     
     
         42 . The system of  claim 41 , wherein the super queue to log, in the shadow segment, a time stamp for the inbound write and a result code. 
     
     
         43 . The system of  claim 42 , wherein the super queue is further to log, in the shadow segment, the inbound data associated with the inbound write. 
     
     
         44 . The system of  claim 38 , further comprising circuitry coupled to the interface to capture one or more of asynchronous transactions and snoops.