Inventor · disambiguated record
Robert Rogenmoser
Also filed as: ROGENMOSER ROBERT
18 granted patents·1 pending application·128 citations·filing 1999–2017
94Inventor score
Top patents by PatentIndex Score
19 records- 0196US8811068B1Integrated circuit devices and methodsCLARK LAWRENCE T·Filed 2012·Granted Aug 19, 2014·21 cites·33 claims
- 0294US8816754B1Body bias circuits and methodsSUVOLTA INC·Filed 2012·Granted Aug 26, 2014·23 cites·6 claims
- 0388US8970289B1Circuits and devices for generating bi-directional body bias voltages, and methods thereforSUVOLTA INC·Filed 2013·Granted Mar 3, 2015·9 cites·20 claims
- 0468US9362291B1Integrated circuit devices and methodsMIE FUJITSU SEMICONDUCTOR LTD·Filed 2014·Granted Jun 7, 2016·2 cites·19 claims
- 0568US6976152B2Comparing operands of instructions against a replay scoreboard to detect an instruction replay and copying a replay scoreboard to an issue scoreboardBROADCOM CORP·Filed 2002·Granted Dec 13, 2005·14 cites·31 claims
- 0668US6941334B2Higher precision divide and square root approximationsBROADCOM CORP·Filed 2002·Granted Sep 6, 2005·15 cites·23 claims
- 0764US9741428B2Integrated circuit devices and methodsMIE FUJITSU SEMICONDUCTOR LTD·Filed 2016·Granted Aug 22, 2017·1 cites·1 claims
- 0864US7269714B2Inhibiting of a co-issuing instruction in a processor having different pipeline lengthsBROADCOM CORP·Filed 2002·Granted Sep 11, 2007·10 cites·6 claims
- 0962US8995204B2Circuit devices and methods having adjustable transistor body biasCLARK LAWRENCE T·Filed 2011·Granted Mar 31, 2015·3 cites·29 claims
- 1059US9966130B2Integrated circuit devices and methodsMIE FUJITSU SEMICONDUCTOR LTD·Filed 2017·Granted May 8, 2018·0 cites·10 claims
- 1159US9154123B1Body bias circuits and methodsMIE FUJITSU SEMICONDUCTOR LTD·Filed 2014·Granted Oct 6, 2015·1 cites·16 claims
- 1257US6430099B1Method and apparatus to conditionally precharge a partitioned read-only memory with shared wordlines for low power operationBROADCOM CORP·Filed 2001·Granted Aug 6, 2002·8 cites·28 claims
- 1356US6538943B2Method and apparatus to conditionally precharge a partitioned read-only memory with shared wordlines for low power operationBROADCOM CORP·Filed 2002·Granted Mar 25, 2003·7 cites·40 claims
- 1452US7100064B2Limiting performance in an integrated circuit to meet export restrictionsBROADCOM CORP·Filed 2002·Granted Aug 29, 2006·3 cites·11 claims
- 1542US2005223055A1Method and apparatus to correct leading one predictionROGENMOSER ROBERT·Filed 2005·Application pending·0 cites
- 1641US6671216B2Method and apparatus to conditionally precharge a partitioned read-only memory with shared wordlines for low power operationBROADCOM CORP·Filed 2003·Granted Dec 30, 2003·2 cites·22 claims
- 1741US6271684B1Method and apparatus for stalling OTB domino circuitsINTEL CORP·Filed 1999·Granted Aug 7, 2001·6 cites·19 claims
- 1840US6995600B2Fast and wire multiplexing circuitsBROADCOM CORP·Filed 2001·Granted Feb 7, 2006·3 cites·2 claims
- 1939US6988115B2Method and apparatus to correct leading one predictionBROADCOM CORP·Filed 2001·Granted Jan 17, 2006·0 cites·22 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →