US2005223055A1PendingUtilityA1

Method and apparatus to correct leading one prediction

Assignee: ROGENMOSER ROBERTPriority: May 4, 2001Filed: Jun 7, 2005Published: Oct 6, 2005
Est. expiryMay 4, 2021(expired)· nominal 20-yr term from priority
G06F 7/485G06F 7/74
42
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Claims

Abstract

A leading one correction circuit receives a significand from a floating point adder and a corresponding leading one prediction from a leading one predictor, and determines if the leading one prediction is correct. In one embodiment, the leading one prediction is a one hot vector having the same number of bits as the significand, with the set bit in the position predicted to have the leading one. In such an embodiment, the leading one correction circuit may perform a bitwise AND of the significand and leading one prediction, and the result of the bitwise AND may be ORed to generate a signal indicating whether or not the prediction is correct. In one implementation, the leading one correction circuit may operate concurrent with a shift of the significand in response to a shift amount indicated by the leading one prediction.

Claims

exact text as granted — not AI-modified
1 . An apparatus for use with an adder configured to generate a value and a leading one predictor configured to generate a leading one prediction corresponding to the value, the apparatus comprising a circuit coupled to receive the value and the leading one prediction, wherein the circuit is configured to generate an indication of whether or not the leading one prediction is correct responsive to the value and the leading one prediction.  
   
   
       2 . The apparatus as recited in  claim 1  further comprising a shifter coupled to receive the value and a shift amount indicated by the leading one prediction, wherein the shifter is configured to shift the value responsive to the shift amount to produce a shift result, and wherein the shifter shifts the value concurrent with the circuit generating the indication.  
   
   
       3 . The apparatus as recited in  claim 2  further comprising a second shifter coupled to receive the shift result and the indication, and wherein the second shifter is configured to shift the shift result one bit if the indication indicates that the leading one prediction is not correct.  
   
   
       4 - 26 . (canceled)

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