Inventor · disambiguated record
Joseph Doller
Also filed as: DOLLER JOSEPH · DOLLER JOSEPH F
3 granted patents·2 pending applications·17 citations·filing 2015–2025
62Inventor score
Technology areasG11C
Top patents by PatentIndex Score
5 records- 0190US9679658B2Method and apparatus for reducing read latency for a block erasable non-volatile memoryINTEL CORP·Filed 2015·Granted Jun 13, 2017·15 cites·20 claims
- 0277US11462273B2SSD with reduced secure erase time and endurance stressINTEL CORP·Filed 2020·Granted Oct 4, 2022·2 cites·15 claims
- 0373US2025342886A1Read latency reduction for partially-programmed block of non-volatile memoryIntel NDTM US LLC·Filed 2025·Application pending·0 cites
- 0453US12362016B2Read latency reduction for partially-programmed block of non-volatile memoryIntel NDTM US LLC·Filed 2020·Granted Jul 15, 2025·0 cites·21 claims
- 0551US2023099202A1Ssd with reduced secure erase time and endurance stressSK HYNIX NAND PRODUCT SOLUTIONS CORP DBA SOLIDIGM·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →