Ssd with reduced secure erase time and endurance stress

Abstract

An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to set an erase voltage for a first block of a persistent storage media to a default erase voltage, determine if the first block of the persistent storage media is identified for a secure erase operation, and set the erase voltage for the first block of the persistent storage media to a shallow erase voltage if the first block of the persistent storage media is identified for the secure erase operation, where the shallow erase voltage corresponds to a weaker erase operation relative to the default erase voltage. Other embodiments are disclosed and claimed.

1 . An electronic apparatus, comprising:
 one or more substrates; and   logic coupled to the one or more substrates, the logic configured to:
 set an erase voltage for a first block of a persistent storage media to a default erase voltage, 
 determine if the first block of the persistent storage media is identified for a secure erase operation, and 
 set the erase voltage for the first block of the persistent storage media to a shallow erase voltage if the first block of the persistent storage media is identified for the secure erase operation, where the shallow erase voltage corresponds to a weaker erase operation relative to the default erase voltage, where the shallow erase voltage corresponds to a more shallow erase distribution relative to the default erase voltage, where the shallow erase voltage is between the default erase voltage and an erase dwell time control state voltage. 
   
     
     
         2 - 20 . (canceled) 
     
     
         21 . The apparatus of  claim 1 , wherein the logic is further configured to:
 perform an erase operation on the first block;   determine if the first block is erased; and   place the first block in an erase dwell time control state and set the erase voltage for the first block back to the default erase voltage, if the first block is determined to be erased.   
     
     
         22 . The apparatus of  claim 21 , wherein the erase dwell time control state voltage is a program voltage associated with the erase dwell time control state. 
     
     
         23 . The apparatus of  claim 1 , wherein the logic is further configured to:
 set an erase voltage for one or more blocks of the persistent storage media in addition to the first block to the default erase voltage;   identify the one or more blocks of the persistent storage media for the secure erase operation;   set the erase voltage for the identified one or more blocks to the shallow erase voltage; and   perform an erase operation on the identified one or more blocks.   
     
     
         24 . The apparatus of  claim 23 , wherein the logic is further configured to:
 determine if all of the identified one or more blocks are erased; and   place the identified one or more blocks in an erase dwell time control state and set the erase voltage for the identified one or more blocks back to the default erase voltage, if all of the identified one or more blocks are determined to be erased.   
     
     
         25 . The apparatus of  claim 1 , wherein the persistent storage media comprises one or more memory die, and wherein the logic is further configured to:
 identify one or more blocks of the persistent storage media, in addition to the first block, for the secure erase operation in response to a command, and for each memory die that includes at least one block of the identified one or more blocks:
 set an erase voltage on the memory die to the shallow erase voltage; 
 perform an erase operation for each of the identified one or more blocks on the memory die after the erase voltage on the memory die is set to the shallow erase voltage; 
 determine if all of the identified one or more blocks on the memory die are erased; and 
 place all of the identified one or more blocks on the memory die in an erase dwell time control state and set the erase voltage on the memory die for the identified one or more blocks on the memory die back to the default erase voltage after all of the identified one or more blocks on the memory die are determined to be erased. 
   
     
     
         26 . The apparatus of  claim 1 , wherein the persistent storage media is part of a solid state drive. 
     
     
         27 . The apparatus of  claim 1 , wherein the persistent storage media is part of NAND-based a solid state drive, and
 wherein the logic is further configured, for the secure erase operation, to change internal NAND trims of the first block to force the more shallow erase distribution relative to the default erase voltage.   
     
     
         28 . An electronic storage system, comprising:
 persistent storage media; and   a controller communicatively coupled to the persistent storage media, the controller including logic configured to:
 set an erase voltage for a first block of the persistent storage media to a default erase voltage, 
 determine if the first block of the persistent storage media is identified for a secure erase operation, and 
 set the erase voltage for the first block of the persistent storage media to a shallow erase voltage if the first block of the persistent storage media is identified for the secure erase operation, where the shallow erase voltage corresponds to a weaker erase operation relative to the default erase voltage, and where the shallow erase voltage corresponds to a more shallow erase distribution relative to the default erase voltage, wherein the shallow erase voltage is between the default erase voltage and an erase dwell time control state voltage. 
   
     
     
         29 . The system of  claim 28 , wherein the logic is further configured to:
 perform an erase operation on the first block;   determine if the first block is erased; and   place the first block in an erase dwell time control state and set the erase voltage for the first block back to the default erase voltage, if the first block is determined to be erased,   wherein the erase dwell time control state voltage is a program voltage associated with the erase dwell time control state.   
     
     
         30 . The system of  claim 28 , wherein the logic is further configured to:
 set an erase voltage for one or more blocks of the persistent storage media in addition to the first block to the default erase voltage;   identify the one or more blocks of the persistent storage media for the secure erase operation;   set the erase voltage for the identified one or more blocks to the shallow erase voltage; and   perform an erase operation on the identified one or more blocks.   
     
     
         31 . The system of  claim 28 , wherein the logic is further configured to:
 determine if all of the identified one or more blocks are erased; and   place the identified one or more blocks in an erase dwell time control state and set the erase voltage for the identified one or more blocks back to the default erase voltage, if all of the identified one or more blocks are determined to be erased.   
     
     
         32 . The system of  claim 28 , wherein the persistent storage media comprises one or more memory die, and wherein the logic is further configured to:
 identify one or more blocks of the persistent storage media, in addition to the first block, for the secure erase operation in response to a command, and for each memory die that includes at least one block of the identified one or more blocks:   set an erase voltage on the memory die to the shallow erase voltage;   perform an erase operation for each of the identified one or more blocks on the memory die after the erase voltage on the memory die is set to the shallow erase voltage;   determine if all of the identified one or more blocks on the memory die are erased; and   place all of the identified one or more blocks on the memory die in an erase dwell time control state and set the erase voltage on the memory die for the identified one or more blocks on the memory die back to the default erase voltage after all of the identified one or more blocks on the memory die are determined to be erased.   
     
     
         33 . The system of  claim 28 , wherein the persistent storage media and controller are part of a solid state drive. 
     
     
         34 . The system of  claim 28 , wherein the persistent storage media is part of NAND-based a solid state drive, and
 wherein the logic is further, for the secure erase operation, to change internal NAND trims of the first block to force the more shallow erase distribution relative to the default erase voltage.   
     
     
         35 . A method of controlling storage, comprising:
 setting an erase voltage for a first block of a persistent storage media to a default erase voltage;   determining the first block of the persistent storage media is identified for a secure erase operation; and   setting the erase voltage for the first block of the persistent storage media to a shallow erase voltage when the first block of the persistent storage media is identified for the secure erase operation, where the shallow erase voltage corresponds to a weaker erase operation relative to the default erase voltage, and where the shallow erase voltage corresponds to a more shallow erase distribution relative to the default erase voltage, wherein the shallow erase voltage is between the default erase voltage and an erase dwell time control state voltage.   
     
     
         36 . The method of  claim 35 , further comprising:
 performing an erase operation on the first block;   determining if the first block is erased; and   placing the first block in an erase dwell time control state and setting the erase voltage for the first block back to the default erase voltage, if the first block is determined to be erased,   wherein the erase dwell time control state voltage is a program voltage associated with the erase dwell time control state.   
     
     
         37 . The method of  claim 35 , further comprising:
 setting an erase voltage for one or more blocks of the persistent storage media in addition to the first block to the default erase voltage;   identifying the one or more blocks of the persistent storage media for the secure erase operation;   setting the erase voltage for the identified one or more blocks to the shallow erase voltage; and   performing an erase operation on the identified one or more blocks.   
     
     
         38 . The method of  claim 35 , further comprising:
 determining if all of the identified one or more blocks are erased; and   placing the identified one or more blocks in an erase dwell time control state and setting the erase voltage for the identified one or more blocks back to the default erase voltage, if all of the identified one or more blocks are determined to be erased.   
     
     
         39 . The method of  claim 35 , wherein the persistent storage media comprises one or more memory die, further comprising:
 identifying one or more blocks of the persistent storage media, in addition to the first block, for the secure erase operation in response to a command, and for each memory die that includes at least one block of the identified one or more blocks:   setting an erase voltage on the memory die to the shallow erase voltage;   performing an erase operation for each of the identified one or more blocks on the memory die after the erase voltage on the memory die is set to the shallow erase voltage;   determining if all of the identified one or more blocks on the memory die are erased; and   placing all of the identified one or more blocks on the memory die in an erase dwell time control state and set the erase voltage on the memory die for the identified one or more blocks on the memory die back to the default erase voltage after all of the identified one or more blocks on the memory die are determined to be erased.