Inventor · disambiguated record
Ja-Hum Ku
Also filed as: KU JA H · KU JA-HUM
44 granted patents·14 pending applications·551 citations·filing 1998–2018
98Inventor score
Top patents by PatentIndex Score
58 records- 0197US9508727B2Integrated circuit device and method of manufacturing the samePARK HONG-BAE·Filed 2015·Granted Nov 29, 2016·48 cites·23 claims
- 0295US10014304B2Integrated circuit device and method of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Jul 3, 2018·10 cites·16 claims
- 0394US7911001B2Methods for forming self-aligned dual stress liners for CMOS semiconductor devicesSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Mar 22, 2011·29 cites·13 claims
- 0494US7297584B2Methods of fabricating semiconductor devices having a dual stress linerSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Nov 20, 2007·34 cites·12 claims
- 0592US7514354B2Methods for forming damascene wiring structures having line and plug conductors formed from different materialsSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Apr 7, 2009·25 cites·21 claims
- 0691US7586175B2Semiconductor wafer having embedded electroplating current paths to provide uniform plating over wafer surfaceSAMSUNG ELECTRONICS CO LTD·Filed 2006·Granted Sep 8, 2009·19 cites·14 claims
- 0790US7534678B2Methods of forming CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein and circuits formed therebySAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted May 19, 2009·20 cites·20 claims
- 0890US6383877B1Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layerSAMSUNG ELECTRONICS CO LTD·Filed 2000·Granted May 7, 2002·49 cites·10 claims
- 0989US7615432B2HDP/PECVD methods of fabricating stress nitride structures for field effect transistorsSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Nov 10, 2009·20 cites·16 claims
- 1086US7084061B2Methods of fabricating a semiconductor device having MOS transistor with strained channelSAMSUNG ELECTRONICS CO LTD·Filed 2004·Granted Aug 1, 2006·36 cites·27 claims
- 1184US6624496B2Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layerSAMSUNG ELECTRONICS CO LTD·Filed 2002·Granted Sep 23, 2003·29 cites·6 claims
- 1281US10651179B2Integrated circuit device and method of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted May 12, 2020·2 cites·15 claims
- 1381US6936528B2Method of forming cobalt silicide film and method of manufacturing semiconductor device having cobalt silicide filmSAMSUNG ELECTRONICS CO LTD·Filed 2003·Granted Aug 30, 2005·33 cites·49 claims
- 1479US10134856B2Semiconductor device including contact plug and method of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Nov 20, 2018·3 cites·18 claims
- 1578US8016941B2Method and apparatus for manufacturing a semiconductorINFINEON TECHNOLOGIES AG·Filed 2007·Granted Sep 13, 2011·7 cites·15 claims
- 1678US6329276B1Method of forming self-aligned silicide in semiconductor deviceSAMSUNG ELECTRONICS CO LTD·Filed 1999·Granted Dec 11, 2001·44 cites·13 claims
- 1777US7781276B2Methods of forming CMOS integrated circuits that utilize insulating layers with high stress characteristics to improve NMOS and PMOS transistor carrier mobilitiesSAMSUNG ELECTRONICS CO LTD·Filed 2009·Granted Aug 24, 2010·4 cites·4 claims
- 1876US7465617B2Method of fabricating a semiconductor device having a silicon oxide layer, a method of fabricating a semiconductor device having dual spacers, a method of forming a silicon oxide layer on a substrate, and a method of forming dual spacers on a conductive material layerSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Dec 16, 2008·4 cites·19 claims
- 1975US7544996B2Methods of fabricating a semiconductor device having a metal gate patternSAMSUNG ELECTRONICS CO LTD·Filed 2006·Granted Jun 9, 2009·4 cites·4 claims
- 2075US7109104B2Methods of fabricating a semiconductor device having a metal gate patternSAMSUNG ELECTRONICS LTD CO·Filed 2003·Granted Sep 19, 2006·15 cites·22 claims
- 2172US7816271B2Methods for forming contacts for dual stress liner CMOS semiconductor devicesSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Oct 19, 2010·6 cites·18 claims
- 2272US7781322B2Nickel alloy salicide transistor structure and method for manufacturing sameSAMSUNG ELECTRONICS CO LTD·Filed 2003·Granted Aug 24, 2010·14 cites·34 claims
- 2372US6764961B2Method of forming a metal gate electrodeSAMSUNG ELECTRONICS CO LTD·Filed 2001·Granted Jul 20, 2004·18 cites·7 claims
- 2471US7800134B2CMOS integrated circuit devices having stressed NMOS and PMOS channel regions thereinSAMSUNG ELECTRONICS CO LTD·Filed 2009·Granted Sep 21, 2010·4 cites·7 claims
- 2570US7598572B2Silicided polysilicon spacer for enhanced contact areaIBM·Filed 2006·Granted Oct 6, 2009·4 cites·2 claims
- 2667US7435673B2Methods of forming integrated circuit devices having metal interconnect structures thereinSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Oct 14, 2008·4 cites·16 claims
- 2766US7541288B2Methods of forming integrated circuit structures using insulator deposition and insulator gap filling techniquesSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Jun 2, 2009·2 cites·23 claims
- 2866US7501651B2Test structure of semiconductor deviceSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Mar 10, 2009·2 cites·24 claims
- 2966US7365025B2Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristicsSAMSUNG ELECTRONICS CO LTD·Filed 2006·Granted Apr 29, 2008·2 cites·11 claims
- 3066US7306996B2Methods of fabricating a semiconductor device having a metal gate patternSAMSUNG ELECTRONICS CO LTD·Filed 2006·Granted Dec 11, 2007·2 cites·21 claims
- 3164US7576407B2Devices and methods for constructing electrically programmable integrated fuses for low power applicationsSAMSUNG ELECTRONICS CO LTD·Filed 2006·Granted Aug 18, 2009·4 cites·38 claims
- 3264US7317204B2Test structure of semiconductor deviceSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Jan 8, 2008·2 cites·28 claims
- 3362US6797559B2Method of fabricating semiconductor device having metal conducting layerSAMSUNG ELECTRONICS CO LTD·Filed 2002·Granted Sep 28, 2004·10 cites·20 claims
- 3461US7232756B2Nickel salicide process with reduced dopant deactivationSAMSUNG ELECTRONICS CO LTD·Filed 2004·Granted Jun 19, 2007·9 cites·38 claims
- 3559US6960515B2Method of forming a metal gateSAMSUNG ELECTRONICS CO LTD·Filed 2001·Granted Nov 1, 2005·10 cites·14 claims
- 3655US7772643B2Methods of fabricating semiconductor device having a metal gate patternSAMSUNG ELECTRONICS CO LTD·Filed 2009·Granted Aug 10, 2010·0 cites·20 claims
- 3754US9613002B2Method of calibrating target values and processing systems configured to calibrate the target valuesHAN CHANG-HO·Filed 2013·Granted Apr 4, 2017·1 cites·20 claims
- 3851US7005367B2Method of fabricating a semiconductor device having a silicon oxide layer, a method of fabricating a semiconductor device having dual spacers, a method of forming a silicon oxide layer on a substrate, and a method of forming dual spacers on a conductive material layerSAMSUNG ELECTRONICS CO LTD·Filed 2003·Granted Feb 28, 2006·2 cites·69 claims
- 3951US2008116521A1CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities and Methods of Forming SameSAMSUNG ELECTRONICS CO LTD·Filed 2006·Application pending·0 cites
- 4051US2008029823A1Semiconductor Device Having a Dual Stress Liner and Light Exposure Apparatus for Forming the Dual Stress LinerCHARTERED SEMICONDUCTOR MFG·Filed 2007·Application pending·0 cites
- 4149US6218690B1Transistor having reverse self-aligned structureSAMSUNG ELECTRONICS CO LTD·Filed 1999·Granted Apr 17, 2001·11 cites·9 claims
- 4246US8008177B2Method for fabricating semiconductor device using a nickel salicide processSAMSUNG ELECTRONICS CO LTD·Filed 2003·Granted Aug 30, 2011·4 cites·20 claims
- 4345US7790622B2Methods for removing gate sidewall spacers in CMOS semiconductor fabrication processesSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Sep 7, 2010·0 cites·36 claims
- 4444US2011163387A1Methods for forming self-aligned dual stress liners for cmos semiconductor devicesLEE KYOUNG WOO·Filed 2011·Application pending·0 cites
- 4543US2006163677A1Methods of forming a semiconductor device having a metal gate electrode and associated devicesSAMSUNG ELECTRONICS CO LTD·Filed 2006·Application pending·0 cites
- 4643US2005236715A1Nickel alloy salicide transistor structure and method for manufacturing sameKU JA-HUM·Filed 2005·Application pending·0 cites
- 4742US2008124859A1Methods of Forming CMOS Integrated Circuits Using Gate Sidewall Spacer Reduction TechniquesSUN MIN CHUL·Filed 2006·Application pending·0 cites
- 4842US2006231906A1Structure for measuring gate misalignment and measuring method thereofSAMSUNG ELECTRONICS CO LTD·Filed 2005·Application pending·0 cites
- 4938US7098123B2Methods of forming a semiconductor device having a metal gate electrode and associated devicesSAMSUNG ELECTRONICS CO LTD·Filed 2004·Granted Aug 29, 2006·0 cites·24 claims
- 5038US2006003534A1Salicide process using bi-metal layer and method of fabricating semiconductor device using the sameSAMSUNG ELECTRONICS CO LTD·Filed 2005·Application pending·0 cites
Showing the top 50 of 58 patent records by PatentIndex Score.
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