Nickel alloy salicide transistor structure and method for manufacturing same

Abstract

Provided are exemplary methods for forming a nickel silicide layer and semiconductor devices incorporating a nickel silicide layer that provides increased stability for subsequent processing at temperatures above 450° C. In particular, the nickel silicide layer is formed from a nickel alloy having a minor portion of an alloying metal, such as tantalum, and exhibits reduced agglomeration and retarded the phase transition between NiSi and NiSi 2 to suppress increases in the sheet resistance and improve the utility for use with fine patterns. As formed, the nickel silicide layer includes both a lower layer consisting primarily of nickel and silicon and a thinner upper layer that incorporates the majority of the alloying metal.

1 . A semiconductor device comprising: 
 a semiconductor substrate, the semiconductor substrate including an active area and an isolation area;    a gate electrode structure formed in the active area, the gate electrode structure including an insulating layer formed on the active area and a conductive layer formed on the insulating layer;    first and second doped regions, the doped regions formed in the active area and separated by the gate electrode structure; and    a nickel silicide region on the first and the second doped region and on the gate electrode structure, the nickel silicide region having a lower layer and an upper layer, the lower layer having a first thickness T 1  and a first alloying metal concentration C AM1  and the upper layer having a second thickness T 2  and a second alloying metal concentration C AM2 .    
   
   
       2 . A semiconductor device according to  claim 1 , wherein: 
 the first thickness T 1  is thicker than the second thickness T 2 .    
   
   
       3 . A method of manufacturing a semiconductor device according to  claim 1 , wherein: 
 the first thickness is at least 70% of a sum of the first thickness and the second thickness.    
   
   
       4 . A method of manufacturing a semiconductor device according to  claim 1 , wherein: 
 the first thickness is at least 85% of a sum of the first thickness and the second thickness.    
   
   
       5 . A semiconductor device according to  claim 1 , wherein: 
 the nickel silicide region includes an alloying metal, wherein lower layer has a first alloying metal concentration C AM1  and the upper layer has a second alloying metal concentration C AM2  that satisfy the relationship C AM1 <C AM2 .    
   
   
       6 . A semiconductor device according to  claim 5 , wherein: 
 a ratio of C AM1  and C AM2  is at least 50:1.    
   
   
       7 . A semiconductor device according to  claim 6 , wherein: 
 a ratio of C Ni1  and C AM1  is at least 100:1.    
   
   
       8 . A semiconductor device according to  claim 7 , wherein: 
 the alloying metal is at least one metal selected from a group consisting of tantalum, vanadium, zirconium, hafnium, tungsten, cobalt, platinum, chromium, palladium, niobium and combinations thereof.    
   
   
       9 . A semiconductor device according to  claim 8 , wherein: the alloying metal is tantalum.  
   
   
       10 . A semiconductor device according to claim  43 , wherein: 
 the lower layer has a tantalum concentration no greater than about 4.9 atomic percent; and    the upper layer has a tantalum concentration of at least about 5 atomic percent.    
   
   
       11 . A semiconductor device according to  claim 9 , wherein: 
 the lower layer has a tantalum concentration no greater than about 0.5 atomic percent; and    the upper layer has a tantalum concentration no greater than 60 percent.    
   
   
       12 . A semiconductor device comprising: 
 a semiconductor substrate, the semiconductor substrate including an active area and an isolation area;    a gate electrode structure formed in the active area, the gate electrode structure including an insulating layer formed on the active area and a conductive layer formed on the insulating layer;    first and second doped regions, the doped regions formed in the active area and separated by the gate electrode structure; and    a nickel silicide region on the first and the second region, the nickel silicide region having a lower layer and an upper layer, the lower layer having a first thickness T 1  and a first alloying metal concentration C AM1  and the upper layer having a second thickness T 2  and a second alloying metal concentration C AM2 .    
   
   
       13 . A semiconductor device according to  claim 12 , wherein: 
 the first thickness T 1  is thicker than the second thickness T 2 .    
   
   
       14 . A method of manufacturing a semiconductor device according to  claim 12 , wherein: 
 the first thickness is at least 70% of a sum of the first thickness and the second thickness.    
   
   
       15 . A method of manufacturing a semiconductor device according to  claim 12 , wherein: 
 the first thickness is at least 85% of a sum of the first thickness and the second thickness.    
   
   
       16 . A semiconductor device according to  claim 12 , wherein: 
 the nickel silicide region includes an alloying metal, wherein lower layer has a first alloying metal concentration C AM1  and the upper layer has a second alloying metal concentration CAM 2  that satisfy the relationship C AM1 <C AM2 .    
   
   
       17 . A semiconductor device according to  claim 16 , wherein: 
 a ratio of C AM1  and C AM2  is at least 50:1.    
   
   
       18 . A semiconductor device according to  claim 17 , wherein: 
 a ratio of C Ni1  and C AM1  is at least 100:1.    
   
   
       19 . A semiconductor device according to  claim 18 , wherein: 
 the alloying metal is at least one metal selected from a group consisting of tantalum, vanadium, zirconium, hafnium, tungsten, cobalt, platinum, chromium, palladium, niobium and combinations thereof.    
   
   
       20 . A semiconductor device according to  claim 19 , wherein: 
 the alloying metal is tantalum.    
   
   
       21 . A semiconductor device according to  claim 20 , wherein: 
 the lower layer has a tantalum concentration no greater than about 4.9 atomic percent; and    the upper layer has a tantalum concentration of at least about 5 atomic percent.    
   
   
       22 . A semiconductor device according to  claim 21 , wherein: 
 the lower layer has a tantalum concentration no greater than about 0.5 atomic percent; and    the upper layer has a tantalum concentration no greater than 60 percent.    
   
   
       23 . A semiconductor device comprising: 
 a semiconductor substrate, the semiconductor substrate including an active area and an isolation area;    a gate electrode structure formed in the active area, the gate electrode structure including an insulating layer formed on the active area and a conductive layer formed on the insulating layer;    first and second doped regions, the doped regions formed in the active area and separated by the gate electrode structure; and    a nickel silicide region on the gate structure, the nickel silicide region having a lower layer and an upper layer, the lower layer having a first thickness T 1  and a first alloying metal concentration C AM1  and the upper layer having a second thickness T 2  and a second alloying metal concentration C AM2  .    
   
   
       24 . A semiconductor device according to  claim 23 , wherein: 
 the first thickness T 1  is thicker than the second thickness T 2 .    
   
   
       25 . A method of manufacturing a semiconductor device according to  claim 23 , wherein: 
 the first thickness is at least 70% of a sum of the first thickness and the second thickness.    
   
   
       26 . A method of manufacturing a semiconductor device according to  claim 23  wherein: 
 the first thickness is at least 85% of a sum of the first thickness and the second thickness.    
   
   
       27 . A semiconductor device according to  claim 23 , wherein: 
 the nickel silicide region includes an alloying metal, wherein lower layer has a first alloying metal concentration C AM1  and the upper layer has a second alloying metal concentration C AM2  that satisfy the relationship C AM1 <C AM2 .    
   
   
       28 . A semiconductor device according to  claim 27 , wherein: 
 a ratio of C AM1  and C AM2  is at least 50:1.    
   
   
       29 . A semiconductor device according to  claim 28 , wherein: 
 a ratio of C Ni1  and C AM1  is at least 100:1.    
   
   
       30 . A semiconductor device according to  claim 29 , wherein: 
 the alloying metal is at least one metal selected from a group consisting of tantalum, vanadium, zirconium, hafnium, tungsten, cobalt, platinum, chromium, palladium, niobium and combinations thereof.    
   
   
       31 . A semiconductor device according to  claim 30 , wherein: 
 the alloying metal is tantalum.    
   
   
       32 . A semiconductor device according to  claim 31 , wherein: 
 the lower layer has a tantalum concentration no greater than about 4.9 atomic percent; and    the upper layer has a tantalum concentration of at least about 5 atomic percent.    
   
   
       33 . A semiconductor device according to  claim 31 , wherein: 
 the lower layer has a tantalum concentration no greater than about 0.5 atomic percent; and    the upper layer has a tantalum concentration no greater than 60 percent.