CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities and Methods of Forming Same

Abstract

A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors.

1 . An integrated circuit device, comprising:
 a semiconductor substrate;   an NMOS transistor in said semiconductor substrate; and   a first electrically insulating layer on said NMOS transistor, said first electrically insulating layer having a sufficiently high internal stress characteristic to impart a tensile stress in a range from about 2 gigapascals to about 4 gigapascals in a channel region of said NMOS transistor.   
   
   
       2 . The device of  claim 1 , further comprising:
 a PMOS transistor in said semiconductor substrate; and   a second electrically insulating layer on said PMOS transistor, said second electrically insulating layer having a sufficiently high internal stress characteristic to impart a compressive stress in a range from about 2 gigapascals to about 4 gigapascals in a channel region of said PMOS transistor.   
   
   
       3 . The device of  claim 2 , wherein said first and second electrically insulating layers comprise the same dielectric material. 
   
   
       4 . The device of  claim 2 , wherein said first electrically insulating layer is a dielectric material selected from a group consisting of SiN, SiON, SiCN, SiC and SiO 2  and combinations thereof. 
   
   
       5 . The device of  claim 1 , further comprising:
 a PMOS transistor in said semiconductor substrate; and   a second electrically insulating layer on said PMOS transistor, said second electrically insulating layer having a sufficiently high internal stress characteristic to impart a compressive stress in a channel region of said PMOS transistor.   
   
   
       6 . The device of  claim 5 , wherein said first and second electrically insulating layers comprise the same dielectric material. 
   
   
       7 . The device of  claim 5 , wherein said first electrically insulating layer is a dielectric material selected from a group consisting of SiN, SiON, SiCN, SiC and SiO 2  and combinations thereof. 
   
   
       8 . A method of forming an integrated circuit device, comprising the steps of:
 forming NMOS and PMOS transistors in a surface of a semiconductor wafer;   depositing a first electrically insulating layer on the NMOS and PMOS transistors and the surface while simultaneously bending the semiconductor wafer so that the surface has a concave shape;   selectively removing portions of the first electrically insulating layer from the PMOS transistors; and   depositing a second electrically insulating layer on the PMOS transistors.   
   
   
       9 . The method of  claim 8 , wherein said step of depositing the second electrically insulating layer comprises depositing the second electrically insulating layer on the PMOS transistors and the surface while simultaneously supporting the semiconductor wafer so that the surface is substantially planar. 
   
   
       10 . The method of  claim 9 , wherein the first and second electrically insulating layers comprise the same dielectric material. 
   
   
       11 . The method of  claim 10 , wherein the first electrically insulating layer is a dielectric material selected from a group consisting of SiN, SiON, SiCN, SiC and SiO 2  and combinations thereof. 
   
   
       12 . The method of  claim 8 , wherein said step of depositing a first electrically insulating layer comprises bending the semiconductor wafer to a sufficient degree so that the first electrically insulating layer has an internal tensile stress in a range from about 2 gigapascals to about 4 gigapascals when the surface is returned to a substantially planar condition. 
   
   
       13 . A semiconductor device comprising:
 a semiconductor substrate;   an NMOS transistor formed on the semiconductor substrate; and   a tensile stress film disposed on the NMOS transistor and applying a tensile stress of 2 to 4 GPa to a channel region of the NMOS transistor.   
   
   
       14 . The semiconductor device of  claim 13 , further comprising a PMOS transistor formed on the semiconductor substrate. 
   
   
       15 . The semiconductor device of  claim 14 , further comprising a compressive stress film formed on the PMOS transistor. 
   
   
       16 . The semiconductor device of  claim 15 , wherein the compressive stress film applies a compressive stress of 2 to 4 GPa to a channel region of the PMOS transistor. 
   
   
       17 . The semiconductor device of  claim 13 , wherein the tensile stress film is formed of SiN, SiON, SiC, SiCN, SiO 2 , or a combination thereof. 
   
   
       18 .- 33 . (canceled)