Inventor · disambiguated record
Stephen Kornachuk
Also filed as: KORNACHUK STEPHEN
9 granted patents·3 pending applications·451 citations·filing 2007–2017
91Inventor score
Top patents by PatentIndex Score
12 records- 0199US8701071B2Enforcement of semiconductor structure regularity for localized transistors and interconnectTELA INNOVATIONS INC·Filed 2013·Granted Apr 15, 2014·64 cites·20 claims
- 0298US9202779B2Enforcement of semiconductor structure regularity for localized transistors and interconnectTELA INNOVATIONS INC·Filed 2014·Granted Dec 1, 2015·42 cites·21 claims
- 0397US8453094B2Enforcement of semiconductor structure regularity for localized transistors and interconnectKORNACHUK STEPHEN·Filed 2009·Granted May 28, 2013·95 cites·22 claims
- 0497US8448102B2Optimizing layout of irregular structures in regular layout contextKORNACHUK STEPHEN·Filed 2009·Granted May 21, 2013·105 cites·26 claims
- 0594US8225261B2Methods for defining contact grid in dynamic array architectureHONG JOSEPH·Filed 2009·Granted Jul 17, 2012·109 cites·29 claims
- 0687US9754878B2Semiconductor chip including a chip level based on a layout that includes both regular and irregular wiresTELA INNOVATIONS INC·Filed 2013·Granted Sep 5, 2017·7 cites·22 claims
- 0786US7577049B1Speculative sense enable tuning apparatus and associated methodsTELA INNOVATIONS INC·Filed 2007·Granted Aug 18, 2009·16 cites·40 claims
- 0884US9530734B2Enforcement of semiconductor structure regularity for localized transistors and interconnectTELA INNOVATIONS INC·Filed 2015·Granted Dec 27, 2016·3 cites·19 claims
- 0979US7586800B1Memory timing apparatus and associated methodsTELA INNOVATIONS INC·Filed 2007·Granted Sep 8, 2009·10 cites·31 claims
- 1056US2017098602A1Enforcement of Semiconductor Structure Regularity for Localized Transistors and InterconnectTELA INNOVATIONS INC·Filed 2016·Application pending·0 cites
- 1152US2017365548A1Optimizing Layout of Irregular Structures in Regular Layout ContextTELA INNOVATIONS INC·Filed 2017·Application pending·0 cites
- 1240US2011156167A1Methods for Consumption of Timing Margin to Reduce Power Utilization in Integrated Circuitry and Device Implementing the SameTELA INNOVATIONS INC·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →