Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect

Abstract

A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a first gate conductive structure defined in a gate level of the semiconductor device, the first gate conductive structure having a linear-shape and a lengthwise centerline oriented in a first direction parallel to a substrate of the semiconductor device;   a second gate conductive structure defined in the gate level of the semiconductor device, the second gate conductive structure having a linear-shape and a lengthwise centerline oriented in the first direction, the lengthwise centerline of the second gate conductive structure separated from the lengthwise centerline of the first gate conductive structure by a first distance as measured in a second direction, the second direction oriented perpendicular to the first direction and parallel to the substrate of the semiconductor device;   a first diffusion region positioned along a portion of a first side of the first gate conductive structure;   a second diffusion region positioned along a portion of a second side of the first gate conductive structure, the second diffusion region also positioned along a portion of a first side of the second gate conductive structure, wherein the first gate conductive structure and the first diffusion region and the second diffusion region together form a first transistor;   a third diffusion region positioned along a portion of a second side of the third gate conductive structure, wherein the second gate conductive structure and the second diffusion region and the third diffusion region together form a second transistor;   a first interconnect conductive structure defined in an interconnect level of the semiconductor device, the interconnect level of the semiconductor device positioned above the gate level of the semiconductor device, the first interconnect conductive structure having a linear-shape and a lengthwise centerline oriented in the first direction, the lengthwise centerline of the first interconnect conductive structure separated from the lengthwise centerline of the first gate conductive structure by one-half of the first distance as measured in the second direction, the first interconnect conductive structure having a width measured in the second direction that is at least twice a width of the first gate conductive structure as measured in the second direction;   a second interconnect conductive structure defined in the interconnect level of the semiconductor device, the second interconnect conductive structure having a linear-shape and a lengthwise centerline oriented in the first direction, the lengthwise centerline of the second interconnect conductive structure separated from the lengthwise centerline of the first gate conductive structure by one-half of the first distance as measured in the second direction, the lengthwise centerline of the second interconnect conductive structure separated from the lengthwise centerline of the third gate conductive structure by one-half of the first distance as measured in the second direction, the second interconnect conductive structure having a width measured in the second direction that is at least twice the width of the first gate conductive structure as measured in the second direction; and   a third interconnect conductive structure defined in the interconnect level of the semiconductor device, the third interconnect conductive structure having a linear-shape and a lengthwise centerline oriented in the first direction, the lengthwise centerline of the third interconnect conductive structure separated from the lengthwise centerline of the second gate conductive structure by one-half of the first distance as measured in the second direction, the third interconnect conductive structure having a width measured in the second direction that is at least twice the width of the first gate conductive structure as measured in the second direction.   
     
     
         2 . The semiconductor device as recited in  claim 1 , wherein each of the first diffusion region, and the second diffusion region, and the third diffusion region has a substantially equal size as measured in the first direction. 
     
     
         3 . The semiconductor device as recited in  claim 1 , further comprising:
 a first diffusion contact extending between the first diffusion region and the first interconnect conductive structure;   a second diffusion contact extending between the second diffusion region and the second interconnect conductive structure; and   a third diffusion contact extending between the third diffusion region and the third interconnect conductive structure.   
     
     
         4 . The semiconductor device as recited in  claim 3 , wherein a centerpoint of the first diffusion contact is separated from the lengthwise centerline of the first gate conductive structure by one-half of the first distance as measured in the second direction. 
     
     
         5 . The semiconductor device as recited in  claim 4 , wherein a centerpoint of the second diffusion contact is separated from the lengthwise centerline of the first gate conductive structure by one-half of the first distance as measured in the second direction; and
 wherein the centerpoint of the second diffusion contact is separated from the lengthwise centerline of the second gate conductive structure by one-half of the first distance as measured in the second direction.   
     
     
         6 . The semiconductor device as recited in  claim 5 , wherein a centerpoint of the third diffusion contact is separated from the lengthwise centerline of the second gate conductive structure by one-half of the first distance as measured in the second direction. 
     
     
         7 . The semiconductor device as recited in  claim 6 , further comprising:
 a fourth interconnect conductive structure defined in the interconnect level of the semiconductor device, the fourth interconnect conductive structure having a linear-shape and a lengthwise centerline oriented in the first direction, the lengthwise centerline of the fourth interconnect conductive structure separated from the lengthwise centerline of the first interconnect conductive structure by one-half of the first distance as measured in the second direction, the lengthwise centerline of the fourth interconnect conductive structure separated from the lengthwise centerline of the second interconnect conductive structure by one-half of the first distance as measured in the second direction.   
     
     
         8 . The semiconductor device as recited in  claim 7 , the fourth interconnect conductive structure having a width measured in the second direction that is at least twice the width of the first gate conductive structure as measured in the second direction. 
     
     
         9 . The semiconductor device as recited in  claim 7 , wherein the lengthwise centerline of the fourth interconnect conductive structure is co-aligned with the lengthwise centerline of the first gate conductive structure. 
     
     
         10 . The semiconductor device as recited in  claim 9 , further comprising:
 a first gate contact extending between the first gate conductive structure and the fourth interconnect conductive structure.   
     
     
         11 . The semiconductor device as recited in  claim 10 , wherein the first gate contact is substantially centered in the second direction on the first gate conductive structure. 
     
     
         12 . The semiconductor device as recited in  claim 11 , wherein the fourth interconnect conductive structure is positioned to overlap an end of the first gate conductive structure in the first direction. 
     
     
         13 . The semiconductor device as recited in  claim 11 , wherein the fourth interconnect conductive structure is separated from the first interconnect conductive structure by an interconnect level end-to-end spacing as measured in the first direction. 
     
     
         14 . The semiconductor device as recited in  claim 11 , further comprising:
 a third gate conductive structure defined in the gate level of the semiconductor device, the third gate conductive structure having a lengthwise centerline oriented in the first direction, the lengthwise centerline of the third gate conductive structure co-aligned with the lengthwise centerline of the first gate conductive structure;   a fourth gate conductive structure defined in the gate level of the semiconductor device, the fourth gate conductive structure having a lengthwise centerline oriented in the first direction, the lengthwise centerline of the fourth gate conductive structure co-aligned with the lengthwise centerline of the second gate conductive structure;   a fourth diffusion region positioned along a portion of a first side of the third gate conductive structure;   a fifth diffusion region positioned along a portion of a second side of the third gate conductive structure, the fifth diffusion region also positioned along a portion of a first side of the fourth gate conductive structure, wherein the third gate conductive structure and the fourth diffusion region and the fifth diffusion region together form a third transistor; and   a sixth diffusion region positioned along a portion of a second side of the fourth gate conductive structure, wherein the fourth gate conductive structure and the fifth diffusion region and the sixth diffusion region together form a fourth transistor.   
     
     
         15 . The semiconductor device as recited in  claim 14 , wherein the third gate conductive structure is separated from the first gate conductive structure by a gate level end-to-end spacing as measured in the first direction; and
 wherein the fourth gate conductive structure is separated from the second gate conductive structure by the gate level end-to-end spacing as measured in the first direction.   
     
     
         16 . The semiconductor device as recited in  claim 14 , wherein each of the fourth diffusion region, and the fifth diffusion region, and the sixth diffusion region has a substantially equal size as measured in the first direction. 
     
     
         17 . The semiconductor device as recited in  claim 14 , further comprising:
 a fifth interconnect conductive structure defined in the interconnect level of the semiconductor device, the fifth interconnect conductive structure having a linear-shape and a lengthwise centerline oriented in the first direction, the lengthwise centerline of the fifth interconnect conductive structure co-aligned with the lengthwise centerline of the first interconnect conductive structure;   a sixth interconnect conductive structure defined in the interconnect level of the semiconductor device, the sixth interconnect conductive structure having a linear-shape and a lengthwise centerline oriented in the first direction, the lengthwise centerline of the sixth interconnect conductive co-aligned with the lengthwise centerline of the second interconnect conductive structure; and   a seventh interconnect conductive structure defined in the interconnect level of the semiconductor device, the seventh interconnect conductive structure having a linear-shape and a lengthwise centerline oriented in the first direction, the lengthwise centerline of the seventh interconnect conductive structure co-aligned with the lengthwise centerline of the third interconnect conductive structure.   
     
     
         18 . The semiconductor device as recited in  claim 17 , wherein the fifth interconnect conductive structure has a width measured in the second direction that is substantially equal to the width of the first interconnect conductive structure, and
 wherein the sixth interconnect conductive structure has a width measured in the second direction that is substantially equal to the width of the second interconnect conductive structure, and   wherein the seventh interconnect conductive structure has a width measured in the second direction that is substantially equal to the width of the third interconnect conductive structure.   
     
     
         19 . The semiconductor device as recited in  claim 17 , further comprising:
 an eighth interconnect conductive structure defined in the interconnect level of the semiconductor device, the eighth interconnect conductive structure having a linear-shape and a lengthwise centerline oriented in the first direction, the lengthwise centerline of the eighth interconnect conductive structure co-aligned with the lengthwise centerline of the second gate conductive structure; and   a second gate contact extending between the fourth gate conductive structure and the eighth interconnect conductive structure, the second gate contact substantially centered in the second direction on the fourth gate conductive structure.   
     
     
         20 . A method for fabricating a semiconductor device, comprising:
 forming a first gate conductive structure in a gate level of the semiconductor device, the first gate conductive structure having a linear-shape and a lengthwise centerline oriented in a first direction parallel to a substrate of the semiconductor device;   forming a second gate conductive structure in the gate level of the semiconductor device, the second gate conductive structure having a linear-shape and a lengthwise centerline oriented in the first direction, the lengthwise centerline of the second gate conductive structure separated from the lengthwise centerline of the first gate conductive structure by a first distance as measured in a second direction, the second direction oriented perpendicular to the first direction and parallel to the substrate of the semiconductor device;   forming a first diffusion region along a portion of a first side of the first gate conductive structure;   forming a second diffusion region along a portion of a second side of the first gate conductive structure, the second diffusion region also positioned along a portion of a first side of the second gate conductive structure, wherein the first gate conductive structure and the first diffusion region and the second diffusion region together form a first transistor;   forming a third diffusion region along a portion of a second side of the third gate conductive structure, wherein the second gate conductive structure and the second diffusion region and the third diffusion region together form a second transistor;   forming a first interconnect conductive structure in an interconnect level of the semiconductor device, the interconnect level of the semiconductor device formed above the gate level of the semiconductor device, the first interconnect conductive structure having a linear-shape and a lengthwise centerline oriented in the first direction, the lengthwise centerline of the first interconnect conductive structure separated from the lengthwise centerline of the first gate conductive structure by one-half of the first distance as measured in the second direction, the first interconnect conductive structure having a width measured in the second direction that is at least twice a width of the first gate conductive structure as measured in the second direction;   forming a second interconnect conductive structure in the interconnect level of the semiconductor device, the second interconnect conductive structure having a linear-shape and a lengthwise centerline oriented in the first direction, the lengthwise centerline of the second interconnect conductive structure separated from the lengthwise centerline of the first gate conductive structure by one-half of the first distance as measured in the second direction, the lengthwise centerline of the second interconnect conductive structure separated from the lengthwise centerline of the third gate conductive structure by one-half of the first distance as measured in the second direction, the second interconnect conductive structure having a width measured in the second direction that is at least twice the width of the first gate conductive structure as measured in the second direction; and   forming a third interconnect conductive structure in the interconnect level of the semiconductor device, the third interconnect conductive structure having a linear-shape and a lengthwise centerline oriented in the first direction, the lengthwise centerline of the third interconnect conductive structure separated from the lengthwise centerline of the second gate conductive structure by one-half of the first distance as measured in the second direction, the third interconnect conductive structure having a width measured in the second direction that is at least twice the width of the first gate conductive structure as measured in the second direction.