Inventor · disambiguated record
Stephen E. Greco
Also filed as: GRECO STEPHEN · GRECO STEPHEN E · GRECO STEPHEN EDWARD
65 granted patents·2 pending applications·1,560 citations·filing 1985–2018
99Inventor score
Top patents by PatentIndex Score
67 records- 0198US6140234AMethod to selectively fill recesses with conductive metalIBM·Filed 1998·Granted Oct 31, 2000·403 cites·24 claims
- 0297US6573606B2Chip to wiring interface with single metal alloy layer applied to surface of copper interconnectIBM·Filed 2001·Granted Jun 3, 2003·307 cites·8 claims
- 0397US6451712B1Method for forming a porous dielectric material layer in a semiconductor device and device formedIBM·Filed 2000·Granted Sep 17, 2002·123 cites·43 claims
- 0491US9589911B1Integrated circuit structure with metal crack stop and methods of forming sameGLOBALFOUNDRIES INC·Filed 2015·Granted Mar 7, 2017·8 cites·12 claims
- 0591US7301236B2Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy viaIBM·Filed 2005·Granted Nov 27, 2007·18 cites·17 claims
- 0689US7071099B1Forming of local and global wiring for semiconductor productIBM·Filed 2005·Granted Jul 4, 2006·18 cites·20 claims
- 0788US9589912B1Integrated circuit structure with crack stop and method of forming sameGLOBALFOUNDRIES INC·Filed 2015·Granted Mar 7, 2017·5 cites·11 claims
- 0888US6917108B2Reliable low-k interconnect structure with hybrid dielectricIBM·Filed 2002·Granted Jul 12, 2005·49 cites·32 claims
- 0987US9455186B2Selective local metal cap layer formation for improved electromigration behaviorIBM·Filed 2015·Granted Sep 27, 2016·4 cites·1 claims
- 1087US7439173B2Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy viaIBM·Filed 2007·Granted Oct 21, 2008·13 cites·13 claims
- 1187US6784105B1Simultaneous native oxide removal and metal neutral deposition methodINFINEON TECHNOLOGIES CORP·Filed 2003·Granted Aug 31, 2004·45 cites·16 claims
- 1286US5444015ALarce scale IC personalization method employing air dielectric structure for extended conductorsIBM·Filed 1994·Granted Aug 22, 1995·77 cites·5 claims
- 1384US8239789B2System and method of predicting problematic areas for lithography in a circuit designBRUNNER TIMOTHY A·Filed 2011·Granted Aug 7, 2012·3 cites·8 claims
- 1483US7488679B2Interconnect structure and process of making the sameIBM·Filed 2006·Granted Feb 10, 2009·13 cites·30 claims
- 1582US5371047AChip interconnection having a breathable etch stop layerIBM·Filed 1992·Granted Dec 6, 1994·73 cites·4 claims
- 1681US9373538B2Interconnect level structures for confining stitch-induced via structuresIBM·Filed 2015·Granted Jun 21, 2016·3 cites·10 claims
- 1781US8806393B1Generation of design shapes for confining stitch-induced via structuresIBM·Filed 2013·Granted Aug 12, 2014·6 cites·20 claims
- 1879US9385038B2Selective local metal cap layer formation for improved electromigration behaviorIBM·Filed 2015·Granted Jul 5, 2016·2 cites·6 claims
- 1979US7645700B2Dry etchback of interconnect contactsIBM·Filed 2007·Granted Jan 12, 2010·5 cites·22 claims
- 2077US7949981B2Via density change to improve wafer surface planarityIBM·Filed 2008·Granted May 24, 2011·7 cites·20 claims
- 2177US5928960AProcess for reducing pattern factor effects in CMP planarizationIBM·Filed 1996·Granted Jul 27, 1999·50 cites·2 claims
- 2275US9075944B2System and method of predicting problematic areas for lithography in a circuit designMENTOR GRAPHICS CORP·Filed 2013·Granted Jul 7, 2015·1 cites·14 claims
- 2375US7368302B2Dynamic metal fill for correcting non-planar regionIBM·Filed 2005·Granted May 6, 2008·4 cites·20 claims
- 2475US6734096B2Fine-pitch device lithography using a sacrificial hardmaskIBM·Filed 2002·Granted May 11, 2004·22 cites·17 claims
- 2574US8484586B2System and method of predicting problematic areas for lithography in a circuit designBRUNNER TIMOTHY A·Filed 2012·Granted Jul 9, 2013·1 cites·20 claims
- 2674US8001495B2System and method of predicting problematic areas for lithography in a circuit designIBM·Filed 2008·Granted Aug 16, 2011·2 cites·10 claims
- 2774US7101784B2Method to generate porous organic dielectricIBM·Filed 2005·Granted Sep 5, 2006·5 cites·20 claims
- 2873US7135398B2Reliable low-k interconnect structure with hybrid dielectricIBM·Filed 2004·Granted Nov 14, 2006·18 cites·28 claims
- 2971US9157980B2Measuring metal line spacing in semiconductor devicesIBM·Filed 2012·Granted Oct 13, 2015·2 cites·19 claims
- 3071US7701035B2Laser fuse structures for high power applicationsIBM·Filed 2005·Granted Apr 20, 2010·5 cites·14 claims
- 3171US7253098B2Maintaining uniform CMP hard mask thicknessIBM·Filed 2004·Granted Aug 7, 2007·13 cites·7 claims
- 3270US6174814B1Method for producing a crack stop for interlevel dielectric layersIBM·Filed 2000·Granted Jan 16, 2001·15 cites·17 claims
- 3369US6091131AIntegrated circuit having crack stop for interlevel dielectric layersIBM·Filed 1998·Granted Jul 18, 2000·33 cites·14 claims
- 3468US7323410B2Dry etchback of interconnect contactsIBM·Filed 2005·Granted Jan 29, 2008·2 cites·8 claims
- 3567US9076847B2Selective local metal cap layer formation for improved electromigration behaviorIBM·Filed 2013·Granted Jul 7, 2015·1 cites·6 claims
- 3667US4600683ACross-linked polyalkenyl phenol based photoresist compositionsIBM·Filed 1985·Granted Jul 15, 1986·27 cites·20 claims
- 3766US6221780B1Dual damascene flowable oxide insulation structure and metallic barrierIBM·Filed 1999·Granted Apr 24, 2001·27 cites·26 claims
- 3865US8053862B2Integrated circuit fuseIBM·Filed 2008·Granted Nov 8, 2011·2 cites·16 claims
- 3965US7941780B2Intersect area based ground rule for semiconductor designIBM·Filed 2008·Granted May 10, 2011·2 cites·25 claims
- 4063US8117568B2Apparatus, method and computer program product for fast simulation of manufacturing effects during integrated circuit designXIANG HUA·Filed 2008·Granted Feb 14, 2012·3 cites·22 claims
- 4163US4997746AMethod of forming conductive lines and studsGRECO NANCY A·Filed 1988·Granted Mar 5, 1991·31 cites·4 claims
- 4262US7300825B2Customizing back end of the line interconnectsIBM·Filed 2004·Granted Nov 27, 2007·10 cites·27 claims
- 4362US6831364B2Method for forming a porous dielectric material layer in a semiconductor device and device formedIBM·Filed 2002·Granted Dec 14, 2004·6 cites·6 claims
- 4460US6727589B2Dual damascene flowable oxide insulation structure and metallic barrierIBM·Filed 2000·Granted Apr 27, 2004·6 cites·24 claims
- 4559US10152567B2Early overlay prediction and overlay-aware mask designIBM·Filed 2018·Granted Dec 11, 2018·0 cites·12 claims
- 4658US6121129AMethod of contact structure formationIBM·Filed 1997·Granted Sep 19, 2000·24 cites·11 claims
- 4758US5530290ALarge scale IC personalization method employing air dielectric structure for extended conductorIBM·Filed 1994·Granted Jun 25, 1996·22 cites·13 claims
- 4857US7456501B1Semiconductor structure having recess with conductive metalIBM·Filed 2000·Granted Nov 25, 2008·4 cites·8 claims
- 4955US7612371B2Structure to monitor arcing in the processing steps of metal layer build on silicon-on-insulator semiconductorsIBM·Filed 2006·Granted Nov 3, 2009·1 cites·11 claims
- 5054US10169525B2Multiple-depth trench interconnect technology at advanced semiconductor nodesIBM·Filed 2017·Granted Jan 1, 2019·0 cites·6 claims
Showing the top 50 of 67 patent records by PatentIndex Score.
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