Inventor · disambiguated record
Douglas M. Reber
Also filed as: REBER DOUGLAS M · REBER DOUGLAS MICHAEL
60 granted patents·15 pending applications·974 citations·filing 1993–2024
98Inventor score
Top patents by PatentIndex Score
75 records- 0198US6531193B2Low temperature, high quality silicon dioxide thin films deposited using tetramethylsilane (TMS) for stress control and coverage applicationsPENN STATE RES FOUND·Filed 2000·Granted Mar 11, 2003·586 cites·27 claims
- 0295US6713381B2Method of forming semiconductor device including interconnect barrier layersMOTOROLA INC·Filed 2002·Granted Mar 30, 2004·135 cites·13 claims
- 0391US9082824B2Method for forming an electrical connection between metal layersREBER DOUGLAS M·Filed 2013·Granted Jul 14, 2015·13 cites·9 claims
- 0491US8601430B1Device matching tool and methods thereofSHROFF MEHUL D·Filed 2012·Granted Dec 3, 2013·13 cites·20 claims
- 0589US9548266B2Semiconductor package with embedded capacitor and methods of manufacturing sameAJURIA SERGIO A·Filed 2014·Granted Jan 17, 2017·20 cites·5 claims
- 0689US9455220B2Apparatus and method for placing stressors on interconnects within an integrated circuit device to manage electromigration failuresSHROFF MEHUL D·Filed 2014·Granted Sep 27, 2016·8 cites·9 claims
- 0788US8946000B2Method for forming an integrated circuit having a programmable fuseFREESCALE SEMICONDUCTOR INC·Filed 2013·Granted Feb 3, 2015·8 cites·19 claims
- 0887US10038081B1Substrate contacts for a transistorNXP USA INC·Filed 2017·Granted Jul 31, 2018·5 cites·20 claims
- 0987US8595667B1Via placement and electronic circuit design processing method and electronic circuit design utilizing sameSHROFF MEHUL D·Filed 2012·Granted Nov 26, 2013·10 cites·6 claims
- 1086US9445050B2Teleconferencing environment having auditory and visual cuesFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Sep 13, 2016·9 cites·9 claims
- 1181US9515006B23D device packaging using through-substrate postsFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Dec 6, 2016·5 cites·20 claims
- 1279US9934349B2Method for verifying design rule checksFREESCALE SEMICONDUCTOR INC·Filed 2015·Granted Apr 3, 2018·5 cites·20 claims
- 1379US9466569B2Though-substrate vias (TSVs) and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Oct 11, 2016·4 cites·18 claims
- 1479US5491871ASolder paste and conductive ink printing stencil cleanerDELCO ELECTRONICS CORP·Filed 1993·Granted Feb 20, 1996·47 cites·4 claims
- 1577US8832624B1Multi-layer process-induced damage tracking and remediationSHROFF MEHUL D·Filed 2013·Granted Sep 9, 2014·4 cites·20 claims
- 1677US8694926B2Techniques for checking computer-aided design layers of a device to reduce the occurrence of missing deck rulesREBER DOUGLAS M·Filed 2012·Granted Apr 8, 2014·4 cites·20 claims
- 1776US9818642B2Method of forming inter-level dielectric structures on semiconductor devicesFREESCALE SEMICONDUCTOR INC·Filed 2015·Granted Nov 14, 2017·2 cites·16 claims
- 1876US6597234B2Anti-fuse circuit and method of operationMOTOROLA INC·Filed 2001·Granted Jul 22, 2003·27 cites·10 claims
- 1974US10522615B2Semiconductor package with embedded capacitor and methods of manufacturing sameNXP USA INC·Filed 2016·Granted Dec 31, 2019·2 cites·9 claims
- 2073US9443804B2Capping layer interface interruption for stress migration mitigationSHROFF MEHUL D·Filed 2013·Granted Sep 13, 2016·3 cites·17 claims
- 2172US9652577B2Integrated circuit design using pre-marked circuit element object libraryTRAVIS EDWARD O·Filed 2014·Granted May 16, 2017·3 cites·11 claims
- 2272US8707231B2Method and system for derived layer checking for semiconductor device designREBER DOUGLAS M·Filed 2012·Granted Apr 22, 2014·3 cites·18 claims
- 2368US10510616B2Post contact air gap formationNXP USA INC·Filed 2017·Granted Dec 17, 2019·1 cites·20 claims
- 2468US8796841B2Semiconductor device with embedded heat spreadingTRAVIS EDWARD O·Filed 2012·Granted Aug 5, 2014·2 cites·17 claims
- 2568US6972255B2Semiconductor device having an organic anti-reflective coating (ARC) and method thereforADVANCED MICRO DEVICES INC·Filed 2003·Granted Dec 6, 2005·10 cites·14 claims
- 2666US9601354B2Semiconductor manufacturing for forming bond pads and seal ringsREBER DOUGLAS M·Filed 2014·Granted Mar 21, 2017·2 cites·12 claims
- 2766US8972922B2Method for forming an electrical connection between metal layersREBER DOUGLAS M·Filed 2013·Granted Mar 3, 2015·1 cites·6 claims
- 2866US8640072B1Method for forming an electrical connection between metal layersREBER DOUGLAS M·Filed 2012·Granted Jan 28, 2014·1 cites·8 claims
- 2965US9508701B23D device packaging using through-substrate pillarsFREESCALE SEMICONDUCTOR INC·Filed 2013·Granted Nov 29, 2016·1 cites·20 claims
- 3063US10008447B2Solar cell powered integrated circuit device and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2015·Granted Jun 26, 2018·1 cites·18 claims
- 3163US9508702B23D device packaging using through-substrate postsFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Nov 29, 2016·1 cites·20 claims
- 3263US9142507B1Stress migration mitigation utilizing induced stress effects in metal trace of integrated circuit deviceFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Sep 22, 2015·1 cites·20 claims
- 3363US6159559ALow temperature, high quality silicon dioxide thin films deposited using tetramethylsilane (TMS)PENN STATE RES FOUND·Filed 1998·Granted Dec 12, 2000·27 cites·14 claims
- 3463US2025385126A1Interconnect structure with relaxed via-corner slopeNXP USA INC·Filed 2024·Application pending·0 cites
- 3562US9318409B1Integrated circuit heater for reducing stress in the integrated circuit material and chip leads of the integrated circuit, and for optimizing performance of devices of the integrated circuitREBER DOUGLAS M·Filed 2014·Granted Apr 19, 2016·1 cites·20 claims
- 3662US2025210464A1Semiconductor circuit with selective backside power and ground distribution and maximum area decoupling capacitorsNXP BV·Filed 2024·Application pending·0 cites
- 3762US2025336718A1Low-k interconnect dielectric by selective implantationNXP USA INC·Filed 2024·Application pending·0 cites
- 3861US10553508B2Semiconductor manufacturing using disposable test circuitry within scribe lanesREBER DOUGLAS M·Filed 2014·Granted Feb 4, 2020·1 cites·5 claims
- 3961US2025261384A1Electronic devices including a sidewall structure and methods of formation thereofNXP BV·Filed 2024·Application pending·0 cites
- 4061US2025210463A1Semiconductor die with buried electrical interconnectionsNXP BV·Filed 2024·Application pending·0 cites
- 4160US8581390B2Semiconductor device with heat dissipationTRAVIS EDWARD O·Filed 2012·Granted Nov 12, 2013·1 cites·20 claims
- 4260US2025140557A1Method for forming a reduced size featureNXP USA INC·Filed 2023·Application pending·0 cites
- 4360US2025185360A1Latch-up prevention with well-tie extension using selective well dopingNXP BV·Filed 2023·Application pending·0 cites
- 4459US2025096039A1Semiconductor wafer fabrication with exposure defined graphene featuresNXP USA INC·Filed 2023·Application pending·0 cites
- 4559US2025063768A1Integrated circuit with overlapping stressorsNXP USA INC·Filed 2023·Application pending·0 cites
- 4659US2025096113A1Semiconductor wafer fabrication with polyimide to graphene conversionNXP USA INC·Filed 2023·Application pending·0 cites
- 4759US2025105171A1Integrated circuit with dielectric layer having selectively implanted stress-setting dopantsNXP USA INC·Filed 2023·Application pending·0 cites
- 4857US9236344B2Thin beam deposited fuseREBER DOUGLAS M·Filed 2014·Granted Jan 12, 2016·0 cites·20 claims
- 4956US10262893B2Method of forming inter-level dielectric structures on semiconductor devicesNXP USA INC·Filed 2017·Granted Apr 16, 2019·0 cites·20 claims
- 5056US6555915B1Integrated circuit having interconnect to a substrate and method thereforMOTOROLA INC·Filed 2001·Granted Apr 29, 2003·7 cites·17 claims
Showing the top 50 of 75 patent records by PatentIndex Score.
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