Electronic devices including a sidewall structure and methods of formation thereof

Abstract

An electronic device including a substrate having a first surface, a second surface, and one or more sidewalls. The electronic device may include a base metallization coupled to the first surface, one or more circuit layers formed on the second surface, and a dielectric layer on the one or more sidewalls and on the one or more circuit layers. The electronic device may include a metal layer formed on the dielectric layer. In some embodiments, one or more of the metal layer or the dielectric layer may form an ionic-contamination barrier. In some implementations, the metal layer, the dielectric layer, and one or more of the substrate or the base metallization layer may form a capacitor that extends around the one or more sides.

What is claimed is: 
     
         1 . A method comprising:
 applying a base metallization layer to a semiconductor substrate of a semiconductor wafer that includes an array of active circuit areas formed on the semiconductor substrate and separated from one another by scribe-lane areas;   cutting the scribe-lane areas of the semiconductor wafer through the semiconductor substrate and partially into the base metallization layer to form scribe-lane trenches including one or more sidewalls;   depositing a dielectric material onto at least a portion of the semiconductor wafer including the one or more sidewalls within the scribe-lane trenches to form a dielectric layer;   depositing a metal layer onto the dielectric layer; and   cutting through the base metallization layer within the scribe-lane trenches to separate the semiconductor wafer into dice.   
     
     
         2 . The method of  claim 1 , wherein the metal layer and the dielectric layer form a perimeter extension that forms a capacitor with one or more of the semiconductor substrate or the base metallization, wherein the capacitor extends around a perimeter of each die. 
     
     
         3 . The method of  claim 1 , wherein cutting through the base metallization layer comprises cutting a center of a bottom extent of each of the scribe-lane trenches to produce one or more scribe-lane extensions. 
     
     
         4 . The method of  claim 3 , wherein each of the one or more scribe-lane extensions has a width that is less than half of a width of one of the scribe-lane trenches. 
     
     
         5 . The method of  claim 3 , wherein cutting the center of the bottom extent of each of the scribe-lane trenches comprises forming the one or more scribe-lane extensions on one or more sidewalls of each die of the array of dice, each scribe-lane extension protruding from one of the one or more sidewalls and including the base metallization layer, the dielectric layer, and the metal layer. 
     
     
         6 . The method of  claim 1 , wherein depositing the dielectric material comprises depositing one or more of tantalum nitride (TaN), hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), or doped tantalum pentoxide (Ta 2 O 5 ). 
     
     
         7 . The method of  claim 1 , wherein the dielectric material that is selected to enable a capacitance per unit area of seventeen femtofarad per micrometer squared or more. 
     
     
         8 . The method of  claim 1 , wherein applying the base metallization layer to the semiconductor substrate comprises applying one or more of aluminum, copper, cobalt, nickel, or tungsten to the semiconductor substrate to form the base metallization layer. 
     
     
         9 . The method of  claim 1 , wherein one or more of the metal layer and the dielectric layer provides an ionic-contamination barrier structure. 
     
     
         10 . An electronic device comprising:
 a semiconductor substrate having a first surface and a second surface;   a base metallization layer formed on the first surface of the semiconductor substrate to form a bottom surface of the electronic device;   one or more circuit layers formed on the second surface of the semiconductor substrate to define a top surface of the electronic device, wherein one or more sidewalls extend between the bottom and top surfaces of the electronic device;   a dielectric layer on the one or more sidewalls; and   a metal layer on the dielectric layer.   
     
     
         11 . The electronic device of  claim 10 , wherein:
 the one or more circuit layers includes a conductive pad on the top surface;   the metal layer is coupled to the conductive pad through the dielectric layer; and   the base metallization layer and the semiconductor substrate are configured to be coupled to one of a negative supply voltage (VSS) or ground and are capacitively coupled to the metal layer through the dielectric layer.   
     
     
         12 . The electronic device of  claim 10 , wherein the metal layer and the dielectric layer extend around the one or more sidewalls to form a capacitor with one or more of the semiconductor substrate or the base metallization layer. 
     
     
         13 . The electronic device of  claim 12 , wherein the capacitor is configured to be coupled to an input/output interface to provide a decoupling function. 
     
     
         14 . The electronic device of  claim 12 , wherein the capacitor is configured to be coupled to a power supply to filter noise from a power supply signal. 
     
     
         15 . The electronic device of  claim 10 , wherein the dielectric layer includes one or more of tantalum nitride (TaN), hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), or doped tantalum pentoxide (Ta 2 O 5 ). 
     
     
         16 . The electronic device of  claim 10 , wherein one or more of the metal layer or the dielectric layer forms an ionic-contamination barrier structure . . . 
     
     
         17 . The electronic device of  claim 10 , wherein the base metallization layer comprises one or more of aluminum, copper, cobalt, nickel, or tungsten. 
     
     
         18 . The electronic device of  claim 10 , further including one or more scribe-lane extensions extending from the one or more sidewalls, each of the one or more scribe-lane extensions including portions of the base metallization layer, the dielectric layer, and the metal layer. 
     
     
         19 . An electronic device comprising:
 a semiconductor substrate including a first surface and a second surface;   a base metallization layer coupled to the first surface of the semiconductor substrate to define a bottom surface of the electronic device; and   one or more circuit layers formed on the second surface of the semiconductor substrate to define a top surface of the electronic device, wherein one or more sidewalls of the electronic device extend between the bottom and top surfaces of the electronic device, and wherein the one or more circuit layers including one or more metal structures forming an active circuit area and including at least one contact pad on the top surface;   a dielectric layer formed on at least a portion of the base metallization layer and on the one or more sidewalls, the dielectric layer including an open area over the at least one contact pad;   a metal layer on the dielectric layer over the sidewalls and coupled to the at least one contact pad.   
     
     
         20 . The electronic device of  claim 19 , wherein:
 the metal layer, the dielectric layer, and one or more of the semiconductor substrate and the base metallization layer form a capacitor that extends around the one or more sidewalls of the semiconductor substrate; and   the capacitor further includes scribe-lane extensions protruding from the one or more sidewalls, each of the scribe-lane extensions including the metal layer, the dielectric layer, and the base metallization layer.