Inventor · disambiguated record
Jeffrey P. Soreff
Also filed as: SOREFF JEFFREY · SOREFF JEFFREY P · SOREFF JEFFREY PAUL
19 granted patents·2 pending applications·200 citations·filing 1990–2019
94Inventor score
Technology areasG06F
Top patents by PatentIndex Score
21 records- 0185US7325210B2Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnectIBM·Filed 2005·Granted Jan 29, 2008·17 cites·13 claims
- 0283US8141014B2System and method for common history pessimism relief during static timing analysisFOREMAN ERIC A·Filed 2009·Granted Mar 20, 2012·12 cites·23 claims
- 0381US10394986B2Model order reduction in transistor level timingIBM·Filed 2018·Granted Aug 27, 2019·2 cites·10 claims
- 0476US5365463AMethod for evaluating the timing of digital machines with statistical variability in their delaysIBM·Filed 1990·Granted Nov 15, 1994·73 cites·24 claims
- 0575US8108816B2Device history based delay variation adjustment during static timing analysisFOREMAN ERIC A·Filed 2009·Granted Jan 31, 2012·7 cites·20 claims
- 0671US8607176B2Delay model construction in the presence of multiple input switching eventsSOREFF JEFFREY P·Filed 2011·Granted Dec 10, 2013·5 cites·20 claims
- 0771US8201120B2Timing point selection for a static timing analysis in the presence of interconnect electrical elementsSOREFF JEFFREY P·Filed 2010·Granted Jun 12, 2012·4 cites·21 claims
- 0871US6763504B2Method for reducing RC parasitics in interconnect networks of an integrated circuitIBM·Filed 2002·Granted Jul 13, 2004·20 cites·10 claims
- 0969US6718523B2Reduced pessimism clock gating tests for a timing analysis toolIBM·Filed 2001·Granted Apr 6, 2004·15 cites·34 claims
- 1065US10031988B2Model order reduction in transistor level timingIBM·Filed 2014·Granted Jul 24, 2018·1 cites·15 claims
- 1164US10949593B2Model order reduction in transistor level timingIBM·Filed 2019·Granted Mar 16, 2021·0 cites·11 claims
- 1264US7225419B2Methods for modeling latch transparencyIBM·Filed 2004·Granted May 29, 2007·8 cites·13 claims
- 1360US7191419B2Method of timing model abstraction for circuits containing simultaneously switching internal signalsIBM·Filed 2004·Granted Mar 13, 2007·7 cites·17 claims
- 1458US7870515B2System and method for improved hierarchical analysis of electronic circuitsIBM·Filed 2008·Granted Jan 11, 2011·1 cites·21 claims
- 1557US8655634B2Modeling loading effects of a transistor networkHATHAWAY DAVID J·Filed 2010·Granted Feb 18, 2014·1 cites·17 claims
- 1651US7552040B2Method and system for modeling logical circuit blocks including transistor gate capacitance loading effectsIBM·Filed 2003·Granted Jun 23, 2009·2 cites·5 claims
- 1751US2008177517A1Techniques for calculating circuit block delay and transition times including transistor gate capacitance loading effectsDORFMAN BARRY LEE·Filed 2008·Application pending·0 cites
- 1850US7080335B2Methods for modeling latch transparencyIBM·Filed 2003·Granted Jul 18, 2006·1 cites·15 claims
- 1950US6430731B1Methods and apparatus for performing slew dependent signal bounding for signal timing analysisIBM·Filed 1999·Granted Aug 6, 2002·24 cites·43 claims
- 2044US7643981B2Pulse waveform timing in EinsTLT templatesIBM·Filed 2004·Granted Jan 5, 2010·0 cites·18 claims
- 2142US2007234253A1Multiple mode approach to building static timing models for digital transistor circuitsIBM·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →