Inventor · disambiguated record
Paul G. Villarrubia
Also filed as: VILLARRUBIA PAUL · VILLARRUBIA PAUL G · VILLARRUBIA PAUL GERARD
57 granted patents·6 pending applications·770 citations·filing 1996–2022
99Inventor score
Top patents by PatentIndex Score
63 records- 0195US7549137B2Latch placement for high performance and low power circuitsIBM·Filed 2006·Granted Jun 16, 2009·43 cites·12 claims
- 0292US8954912B2Structured placement of latches/flip-flops to minimize clock power in high-performance designsIBM·Filed 2012·Granted Feb 10, 2015·18 cites·25 claims
- 0392US7581201B2System and method for sign-off timing closure of a VLSI chipIBM·Filed 2007·Granted Aug 25, 2009·35 cites·19 claims
- 0491US9754062B2Timing adjustments across transparent latches to facilitate power reductionIBM·Filed 2015·Granted Sep 5, 2017·9 cites·20 claims
- 0590US7624366B2Clock aware placementIBM·Filed 2006·Granted Nov 24, 2009·27 cites·34 claims
- 0689US9483596B1Multi power synthesis in digital circuit designIBM·Filed 2016·Granted Nov 1, 2016·16 cites·20 claims
- 0789US6996512B2Practical methodology for early buffer and wire resource allocationIBM·Filed 2001·Granted Feb 7, 2006·60 cites·21 claims
- 0888US8782584B2Post-placement cell shiftingIBM·Filed 2013·Granted Jul 15, 2014·10 cites·1 claims
- 0987US10528695B1Integer arithmetic method for wire length minimization in global placement with convolution based density penalty computationIBM·Filed 2018·Granted Jan 7, 2020·5 cites·20 claims
- 1087US9495501B1Large cluster persistence during placement optimization of integrated circuit designsIBM·Filed 2016·Granted Nov 15, 2016·4 cites·10 claims
- 1186US10803224B2Propagating constants of structured soft blocks while preserving the relative placement structureIBM·Filed 2018·Granted Oct 13, 2020·5 cites·20 claims
- 1286US10558775B2Memory element graph-based placement in integrated circuit designIBM·Filed 2017·Granted Feb 11, 2020·4 cites·17 claims
- 1384US7996812B2Method of minimizing early-mode violations causing minimum impact to a chip designIBM·Filed 2008·Granted Aug 9, 2011·16 cites·18 claims
- 1482US8826215B1Routing centric design closureIBM·Filed 2013·Granted Sep 2, 2014·6 cites·18 claims
- 1582US8370782B2Buffer-aware routing in integrated circuit designIBM·Filed 2010·Granted Feb 5, 2013·9 cites·30 claims
- 1682US7467369B2Constrained detailed placementIBM·Filed 2006·Granted Dec 16, 2008·13 cites·8 claims
- 1781US9098669B1Boundary latch and logic placement to satisfy timing constraintsIBM·Filed 2014·Granted Aug 4, 2015·7 cites·24 claims
- 1880US11080456B2Automated design closure with abutted hierarchyIBM·Filed 2019·Granted Aug 3, 2021·4 cites·17 claims
- 1979US8954915B2Structured placement of hierarchical soft blocks during physical synthesis of an integrated circuitIBM·Filed 2013·Granted Feb 10, 2015·6 cites·12 claims
- 2079US8495534B2Post-placement cell shiftingALPERT CHARLES J·Filed 2010·Granted Jul 23, 2013·5 cites·23 claims
- 2178US7464356B2Method and apparatus for diffusion based cell placement migrationIBM·Filed 2005·Granted Dec 9, 2008·7 cites·7 claims
- 2277US8347257B2Detailed routability by cell placementIBM·Filed 2010·Granted Jan 1, 2013·5 cites·24 claims
- 2377US8327304B2Partitioning for hardware-accelerated functional verificationMOFFITT MICHAEL D·Filed 2010·Granted Dec 4, 2012·5 cites·20 claims
- 2477US7882475B2Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectorsIBM·Filed 2008·Granted Feb 1, 2011·8 cites·3 claims
- 2577US7047163B1Method and apparatus for applying fine-grained transforms during placement synthesis interactionIBM·Filed 2000·Granted May 16, 2006·25 cites·12 claims
- 2677US6671867B2Analytical constraint generation for cut-based global placementIBM·Filed 2002·Granted Dec 30, 2003·23 cites·21 claims
- 2777US6510540B1Windowing mechanism for reducing pessimism in cross-talk analysis of digital chipsIBM·Filed 2000·Granted Jan 21, 2003·29 cites·28 claims
- 2875US7076755B2Method for successive placement based refinement of a generalized cost functionIBM·Filed 2004·Granted Jul 11, 2006·24 cites·15 claims
- 2973US6080201AIntegrated placement and synthesis for timing closure of microprocessorsIBM·Filed 1998·Granted Jun 27, 2000·74 cites·12 claims
- 3072US7296252B2Clustering techniques for faster and better placement of VLSI circuitsIBM·Filed 2004·Granted Nov 13, 2007·17 cites·18 claims
- 3171US10762271B2Model-based refinement of the placement process in integrated circuit generationIBM·Filed 2018·Granted Sep 1, 2020·1 cites·20 claims
- 3271US10635773B1Enhancing stability of half perimeter wire length (HPWL)-driven analytical placementIBM·Filed 2018·Granted Apr 28, 2020·1 cites·20 claims
- 3370US7073144B2Stability metrics for placement to quantify the stability of placement algorithmsIBM·Filed 2004·Granted Jul 4, 2006·14 cites·27 claims
- 3470US7020861B2Latch placement technique for reduced clock signal skewIBM·Filed 2003·Granted Mar 28, 2006·16 cites·16 claims
- 3569US7089521B2Method for legalizing the placement of cells in an integrated circuit layoutIBM·Filed 2004·Granted Aug 8, 2006·16 cites·19 claims
- 3664US12282725B2Enhanced alignment for global placement in a circuitIBM·Filed 2022·Granted Apr 22, 2025·0 cites·20 claims
- 3764US8799846B1Facilitating the design of a clock grid in an integrated circuitIBM·Filed 2013·Granted Aug 5, 2014·2 cites·20 claims
- 3863US12277375B2Power staple avoidance for routing via reductionIBM·Filed 2022·Granted Apr 15, 2025·0 cites·20 claims
- 3963US11080443B2Memory element graph-based placement in integrated circuit designIBM·Filed 2019·Granted Aug 3, 2021·0 cites·13 claims
- 4063US10685160B2Large cluster persistence during placement optimization of integrated circuit designsIBM·Filed 2018·Granted Jun 16, 2020·0 cites·18 claims
- 4163US5831870AMethod and system for characterizing interconnect data within an integrated circuit for facilitating parasitic capacitance estimationIBM·Filed 1996·Granted Nov 3, 1998·46 cites·15 claims
- 4262US12417333B2Short net pin alignment for routingIBM·Filed 2022·Granted Sep 16, 2025·0 cites·20 claims
- 4359US11916384B2Region-based power grid generation through modification of an initial power grid based on timing analysisIBM·Filed 2021·Granted Feb 27, 2024·0 cites·20 claims
- 4458US6360350B1Method and system for performing circuit analysis on an integrated-circuit design having design data available in different formsIBM·Filed 1997·Granted Mar 19, 2002·39 cites·12 claims
- 4557US10140409B2Large cluster persistence during placement optimization of integrated circuit designsIBM·Filed 2016·Granted Nov 27, 2018·0 cites·5 claims
- 4656US6286007B1Method and system for efficiently storing and viewing data in a databaseIBM·Filed 1998·Granted Sep 4, 2001·33 cites·20 claims
- 4756US5838582AMethod and system for performing parasitic capacitance estimations on interconnect data within an integrated circuitIBM·Filed 1996·Granted Nov 17, 1998·31 cites·13 claims
- 4855US8930867B2Scheduling for parallel processing of regionally-constrained placement problemIBM·Filed 2013·Granted Jan 6, 2015·0 cites·11 claims
- 4955US8245173B2Scheduling for parallel processing of regionally-constrained placement problemNAM GI-JOON·Filed 2009·Granted Aug 14, 2012·1 cites·2 claims
- 5053US6086238AMethod and system for shape processing within an integrated circuit layout for parasitic capacitance estimationIBM·Filed 1996·Granted Jul 11, 2000·27 cites·9 claims
Showing the top 50 of 63 patent records by PatentIndex Score.
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