Inventor · disambiguated record
Thomas G. Sopchak
Also filed as: SOPCHAK THOMAS G · SOPCHAK THOMAS GREGORY
19 granted patents·190 citations·filing 1995–2017
94Inventor score
Top patents by PatentIndex Score
19 records- 0196US7240322B2Method of adding fabrication monitors to integrated circuit chipsIBM·Filed 2005·Granted Jul 3, 2007·60 cites·18 claims
- 0280US7194706B2Designing scan chains with specific parameter sensitivities to identify process defectsIBM·Filed 2004·Granted Mar 20, 2007·24 cites·26 claims
- 0376US9653330B1Threshold voltage (VT)-type transistor sensitive and/or fan-out sensitive selective voltage binningGLOBALFOUNDRIES INC·Filed 2016·Granted May 16, 2017·2 cites·20 claims
- 0473US7323278B2Method of adding fabrication monitors to integrated circuit chipsIBM·Filed 2007·Granted Jan 29, 2008·3 cites·9 claims
- 0570US6998866B1Circuit and method for monitoring defectsIBM·Filed 2004·Granted Feb 14, 2006·13 cites·30 claims
- 0669US7007214B2Diagnosable scan chainIBM·Filed 2003·Granted Feb 28, 2006·14 cites·29 claims
- 0769US5719879AScan-bypass architecture without additional external latchesIBM·Filed 1995·Granted Feb 17, 1998·28 cites·13 claims
- 0868US7285860B2Method and structure for defect monitoring of semiconductor devices using power bus wiring gridsIBM·Filed 2006·Granted Oct 23, 2007·2 cites·3 claims
- 0967US5925143AScan-bypass architecture without additional external latchesIBM·Filed 1997·Granted Jul 20, 1999·27 cites·7 claims
- 1066US7088124B2Utilizing clock shield as defect monitorIBM·Filed 2005·Granted Aug 8, 2006·3 cites·7 claims
- 1164US7620931B2Method of adding fabrication monitors to integrated circuit chipsIBM·Filed 2007·Granted Nov 17, 2009·1 cites·17 claims
- 1263US7005874B2Utilizing clock shield as defect monitorIBM·Filed 2004·Granted Feb 28, 2006·7 cites·14 claims
- 1357US10295592B2Pre-test power-optimized bin reassignment following selective voltage binningGLOBALFOUNDRIES INC·Filed 2017·Granted May 21, 2019·0 cites·17 claims
- 1453US7078248B2Method and structure for defect monitoring of semiconductor devices using power bus wiring gridsIBM·Filed 2004·Granted Jul 18, 2006·3 cites·8 claims
- 1552US9759767B2Pre-test power-optimized bin reassignment following selective voltage binningGLOBALFOUNDRIES INC·Filed 2015·Granted Sep 12, 2017·0 cites·11 claims
- 1644US7239167B2Utilizing clock shield as defect monitorIBM·Filed 2006·Granted Jul 3, 2007·0 cites·20 claims
- 1741US7145977B2Diagnostic method and apparatus for non-destructively observing latch dataIBM·Filed 2003·Granted Dec 5, 2006·2 cites·23 claims
- 1838US7453973B2Diagnostic method and apparatus for non-destructively observing latch dataIBM·Filed 2006·Granted Nov 18, 2008·0 cites·6 claims
- 1938US7089514B2Defect diagnosis for semiconductor integrated circuitsIBM·Filed 2004·Granted Aug 8, 2006·1 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →