Inventor · disambiguated record
Steven F. Oakland
Also filed as: OAKLAND STEVEN F · OAKLAND STEVEN FREDERICK
47 granted patents·6 pending applications·1,005 citations·filing 1988–2015
98Inventor score
Top patents by PatentIndex Score
53 records- 0197US7456674B2Clock generator having improved deskewerIBM·Filed 2008·Granted Nov 25, 2008·38 cites·15 claims
- 0295US6577156B2Method and apparatus for initializing an integrated circuit using compressed data from a remote fuseboxIBM·Filed 2000·Granted Jun 10, 2003·106 cites·28 claims
- 0395US6300809B1Double-edge-triggered flip-flop providing two data transitions per clock cycleIBM·Filed 2000·Granted Oct 9, 2001·68 cites·6 claims
- 0492US6768694B2Method of electrically blowing fuses under control of an on-chip tester interface apparatusIBM·Filed 2002·Granted Jul 27, 2004·84 cites·44 claims
- 0590US6493257B1CMOS state saving latchIBM·Filed 2002·Granted Dec 10, 2002·57 cites·20 claims
- 0689US6304122B1Low power LSSD flip flops and a flushable single clock splitter for flip flopsIBM·Filed 2000·Granted Oct 16, 2001·42 cites·22 claims
- 0789US5920575AVLSI test circuit apparatus and methodIBM·Filed 1997·Granted Jul 6, 1999·74 cites·22 claims
- 0888US5272729AClock signal latency elimination networkIBM·Filed 1991·Granted Dec 21, 1993·142 cites·24 claims
- 0987US6567943B1D flip-flop structure with flush path for high-speed boundary scan applicationsIBM·Filed 2000·Granted May 20, 2003·41 cites·27 claims
- 1087US5311079ALow power, high performance PLADITLOW GARY S·Filed 1992·Granted May 10, 1994·64 cites·4 claims
- 1186US8423847B2Microcontroller for logic built-in self test (LBIST)GRISE GARY D·Filed 2012·Granted Apr 16, 2013·5 cites·17 claims
- 1284US5825785ASerial input shift register built-in self test circuit for embedded circuitsINTERNAITONAL BUSINESS MACHINE·Filed 1996·Granted Oct 20, 1998·63 cites·16 claims
- 1383US7840864B2Functional frequency testing of integrated circuitsIBM·Filed 2009·Granted Nov 23, 2010·8 cites·16 claims
- 1477US7490280B2Microcontroller for logic built-in self test (LBIST)IBM·Filed 2006·Granted Feb 10, 2009·6 cites·10 claims
- 1577US7310278B2Method and apparatus for in-system redundant array repair on integrated circuitsIBM·Filed 2006·Granted Dec 18, 2007·8 cites·8 claims
- 1676US8230283B2Method to test hold path faults using functional clockingGILLIS PAMELA S·Filed 2009·Granted Jul 24, 2012·9 cites·15 claims
- 1775US7560964B2Latch and clock structures for enabling race-reduced MUX scan and LSSD co-compatibilityIBM·Filed 2005·Granted Jul 14, 2009·7 cites·19 claims
- 1871US7840863B2Functional frequency testing of integrated circuitsIBM·Filed 2009·Granted Nov 23, 2010·4 cites·18 claims
- 1970US7482851B2Latch and clock structures for enabling race-reduced mux scan and LSSD co-compatibilityIBM·Filed 2007·Granted Jan 27, 2009·5 cites·11 claims
- 2069US7281182B2Method and circuit using boundary scan cells for design library analysisIBM·Filed 2005·Granted Oct 9, 2007·6 cites·20 claims
- 2169US5719879AScan-bypass architecture without additional external latchesIBM·Filed 1995·Granted Feb 17, 1998·28 cites·13 claims
- 2267US6856270B1Pipeline arrayIBM·Filed 2004·Granted Feb 15, 2005·14 cites·20 claims
- 2367US5925143AScan-bypass architecture without additional external latchesIBM·Filed 1997·Granted Jul 20, 1999·27 cites·7 claims
- 2466US9599664B2Circuit for detecting structural defects in an integrated circuit chip, methods of use and manufacture and design structuresIBM·Filed 2015·Granted Mar 21, 2017·1 cites·19 claims
- 2565US8205124B2Microcontroller for logic built-in self test (LBIST)GRISE GARY D·Filed 2008·Granted Jun 19, 2012·3 cites·26 claims
- 2664US4980889AMulti-mode testing systemsDEGUISE WAYNE J·Filed 1988·Granted Dec 25, 1990·27 cites·18 claims
- 2763US9172373B2Verifying partial good voltage island structuresIBM·Filed 2013·Granted Oct 27, 2015·1 cites·19 claims
- 2862US9057760B2Circuit for detecting structural defects in an integrated circuit chip, methods of use and manufacture and design structuresLACROIX LUKE D·Filed 2011·Granted Jun 16, 2015·1 cites·18 claims
- 2962US7089136B2Method for reduced electrical fusing timeIBM·Filed 2003·Granted Aug 8, 2006·12 cites·17 claims
- 3060US8423844B2Dense register array for enabling scan out observation of both L1 and L2 latchesGILLIS PAMELA S·Filed 2011·Granted Apr 16, 2013·1 cites·14 claims
- 3159US7290191B2Functional frequency testing of integrated circuitsIBM·Filed 2004·Granted Oct 30, 2007·6 cites·18 claims
- 3258US7823035B2System and methods of balancing scan chains and inserting the balanced-length scan chains into hierarchically designed integrated circuitsIBM·Filed 2007·Granted Oct 26, 2010·3 cites·28 claims
- 3358US7428675B2Testing using independently controllable voltage islandsIBM·Filed 2003·Granted Sep 23, 2008·5 cites·18 claims
- 3456US7698611B2Functional frequency testing of integrated circuitsIBM·Filed 2007·Granted Apr 13, 2010·2 cites·24 claims
- 3555US6927614B2High performance state saving circuitIBM·Filed 2003·Granted Aug 9, 2005·6 cites·20 claims
- 3653US2008284459A1Testing Using Independently Controllable Voltage IslandsIBM·Filed 2008·Application pending·0 cites
- 3750US7405990B2Method and apparatus for in-system redundant array repair on integrated circuitsIBM·Filed 2007·Granted Jul 29, 2008·1 cites·5 claims
- 3849US7457187B2Design structure for in-system redundant array repair in integrated circuitsIBM·Filed 2007·Granted Nov 25, 2008·1 cites·12 claims
- 3947US4868413ATestable passgate logic circuitsIBM·Filed 1988·Granted Sep 19, 1989·7 cites·22 claims
- 4047US2008155151A1Programmable Locking Mechanism For Secure Applications In An Integrated CircuitIBM·Filed 2006·Application pending·0 cites
- 4145US7284172B2Access method for embedded JTAG TAP controller instruction registersIBM·Filed 2004·Granted Oct 16, 2007·5 cites·25 claims
- 4243US7404125B2Compilable memory structure and test methodology for both ASIC and foundry test environmentsIBM·Filed 2005·Granted Jul 22, 2008·1 cites·7 claims
- 4342US7243279B2Method for separating shift and scan paths on scan-only, single port LSSD latchesIBM·Filed 2003·Granted Jul 10, 2007·1 cites·20 claims
- 4442US2007200597A1Clock generator having improved deskewerOAKLAND STEVEN F·Filed 2006·Application pending·0 cites
- 4541US7397709B2Method and apparatus for in-system redundant array repair on integrated circuitsIBM·Filed 2007·Granted Jul 8, 2008·0 cites·6 claims
- 4641US6656751B2Self test method and device for dynamic voltage screen functionality improvementIBM·Filed 2001·Granted Dec 2, 2003·3 cites·13 claims
- 4737US8181135B2Hold transition fault model and test generation methodIYENGAR VIKRAM·Filed 2009·Granted May 15, 2012·0 cites·15 claims
- 4837US2008005634A1Scan chain circuitry that enables scan testing at functional clock speedGRISE GARY D·Filed 2006·Application pending·0 cites
- 4937US2008256405A1Compilable memory structure and test methodology for both asic and foundry test environmentsIBM·Filed 2008·Application pending·0 cites
- 5036US2006248417A1Clock control circuit for test that facilitates an at speed structural testIBM·Filed 2005·Application pending·0 cites
Showing the top 50 of 53 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →