Inventor · disambiguated record
Laegu Kang
Also filed as: KANG LAEGU
19 granted patents·2 pending applications·136 citations·filing 1990–2017
93Inventor score
Files withFREESCALE SEMICONDUCTOR INC6GLOBALFOUNDRIES INC6CHEN XIANGDONG2MOTOROLA INC2JEONG YONG-KUK1
Top patents by PatentIndex Score
21 records- 0189US8809178B2Methods of forming bulk FinFET devices with replacement gates so as to reduce punch through leakage currentsLIU YANXIANG·Filed 2012·Granted Aug 19, 2014·13 cites·20 claims
- 0287US8445969B2High pressure deuterium treatment for semiconductor/high-K insulator interfaceCHEN XIANGDONG·Filed 2011·Granted May 21, 2013·8 cites·24 claims
- 0387US6724048B2Body-tied silicon on insulator semiconductor device and method thereforMOTOROLA INC·Filed 2003·Granted Apr 20, 2004·38 cites·5 claims
- 0485US7528078B2Process of forming electronic device including a densified nitride layer adjacent to an opening within a semiconductor layerFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted May 5, 2009·11 cites·20 claims
- 0585US7186596B2Vertical diode formation in SOI applicationFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Mar 6, 2007·13 cites·20 claims
- 0685US6620656B2Method of forming body-tied silicon on insulator semiconductor deviceMOTOROLA INC·Filed 2001·Granted Sep 16, 2003·34 cites·18 claims
- 0772US9099525B2Blanket EPI super steep retrograde well formation without Si recessKANG LAEGU·Filed 2012·Granted Aug 4, 2015·4 cites·11 claims
- 0872US8916442B2Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting deviceGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 23, 2014·2 cites·12 claims
- 0961US7517742B2Area diode formation in SOI applicationFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Apr 14, 2009·2 cites·19 claims
- 1058US8790972B2Methods of forming CMOS transistors using tensile stress layers and hydrogen plasma treatmentJEONG YONG-KUK·Filed 2010·Granted Jul 29, 2014·2 cites·17 claims
- 1157US10483172B2Transistor device structures with retrograde wells in CMOS applicationsGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 19, 2019·0 cites·16 claims
- 1257US9099380B2Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting deviceGLOBALFOUNDRIES INC·Filed 2014·Granted Aug 4, 2015·0 cites·20 claims
- 1353US9852954B2Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structuresGLOBALFOUNDRIES INC·Filed 2015·Granted Dec 26, 2017·0 cites·19 claims
- 1452US9209181B2Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structuresGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 8, 2015·0 cites·10 claims
- 1549US9362357B2Blanket EPI super steep retrograde well formation without Si recessGLOBALFOUNDRIES INC·Filed 2015·Granted Jun 7, 2016·0 cites·20 claims
- 1643US7126172B2Integration of multiple gate dielectrics by surface protectionFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Oct 24, 2006·2 cites·26 claims
- 1741US7795089B2Forming a semiconductor device having epitaxially grown source and drain regionsFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Sep 14, 2010·0 cites·13 claims
- 1841US2007224772A1Method for forming a stressor structureFREESCALE SEMICONDUCTOR INC·Filed 2006·Application pending·0 cites
- 1939US8106462B2Balancing NFET and PFET performance using straining layersCHEN XIANGDONG·Filed 2010·Granted Jan 31, 2012·0 cites·20 claims
- 2038US2014070358A1Method of tailoring silicon trench profile for super steep retrograde well field effect transistorQI YI·Filed 2012·Application pending·0 cites
- 2137US5068200AMethod of manufacturing DRAM cellSAMSUNG ELECTRONICS CO LTD·Filed 1990·Granted Nov 26, 1991·7 cites·1 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →