Inventor · disambiguated record
Shwetal Arvind Patel
Also filed as: PATEL SHWETAL · PATEL SHWETAL A · PATEL SHWETAL ARVIND
13 granted patents·2 pending applications·127 citations·filing 2002–2022
89Inventor score
Files withINTEGRATED DEVICE TECH7ADVANCED MICRO DEVICES INC3RENESAS ELECTRONICS AMERICA INC2DEARTH GLENN A1GLOBALFOUNDRIES INC1
Top patents by PatentIndex Score
15 records- 0190US7421525B2System including a host connected to a plurality of memory modules via a serial memory interconnectADVANCED MICRO DEVICES INC·Filed 2004·Granted Sep 2, 2008·56 cites·16 claims
- 0289US8260992B2Reducing simultaneous switching outputs using data bus inversion signalingDEARTH GLENN A·Filed 2010·Granted Sep 4, 2012·16 cites·19 claims
- 0386US10394460B1Enhanced data buffer and intelligent NV controller for simultaneous DRAM and flash memory accessINTEGRATED DEVICE TECH·Filed 2015·Granted Aug 27, 2019·6 cites·1 claims
- 0483US6957308B1DRAM supporting different burst-length accesses without changing the burst length setting in the mode registerADVANCED MICRO DEVICES INC·Filed 2002·Granted Oct 18, 2005·41 cites·37 claims
- 0567US12475236B2Write protect function with secure certificate authenticationRENESAS ELECTRONICS AMERICA INC·Filed 2022·Granted Nov 18, 2025·0 cites·12 claims
- 0667US8019921B2Intelligent memory bufferGLOBALFOUNDRIES INC·Filed 2008·Granted Sep 13, 2011·4 cites·5 claims
- 0766US10769082B2DDR5 PMIC interface protocol and operationINTEGRATED DEVICE TECH·Filed 2018·Granted Sep 8, 2020·1 cites·20 claims
- 0865US11815978B2DDR5 client PMIC power up sequence and state transitionsRENESAS ELECTRONICS AMERICA INC·Filed 2021·Granted Nov 14, 2023·0 cites·18 claims
- 0960US11249539B2DDR5 client PMIC power up sequence and state transitionsINTEGRATED DEVICE TECH·Filed 2019·Granted Feb 15, 2022·0 cites·19 claims
- 1059US9847112B2Synchronization of data transmission with a clock signal after a memory mode switchINTEGRATED DEVICE TECH·Filed 2016·Granted Dec 19, 2017·1 cites·20 claims
- 1158US9552870B1Memory includes transmitter for data synchronization transmission after a mode switch and method thereofINTEGRATED DEVICE TECH·Filed 2016·Granted Jan 24, 2017·1 cites·20 claims
- 1256US10776293B2DDR5 RCD interface protocol and operationINTEGRATED DEVICE TECH·Filed 2018·Granted Sep 15, 2020·1 cites·20 claims
- 1348US10401899B2Register clock driver for DDR5 memoryINTEGRATED DEVICE TECH·Filed 2017·Granted Sep 3, 2019·0 cites·17 claims
- 1440US2012239887A1Method and apparatus for memory controlMAGRO JAMES R·Filed 2011·Application pending·0 cites
- 1535US2009091963A1Memory deviceADVANCED MICRO DEVICES INC·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →