Inventor · disambiguated record
Vara Govindeswara Reddy Vakada
Also filed as: VAKADA VARA · VAKADA VARA G · VAKADA VARA G REDDY · VAKADA VARA GOVINDESWARA REDDY
14 granted patents·2 pending applications·11 citations·filing 2012–2019
86Inventor score
Top patents by PatentIndex Score
16 records- 0177US9064868B2Advanced faraday shield for a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2012·Granted Jun 23, 2015·4 cites·16 claims
- 0272US9099525B2Blanket EPI super steep retrograde well formation without Si recessKANG LAEGU·Filed 2012·Granted Aug 4, 2015·4 cites·11 claims
- 0372US8916442B2Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting deviceGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 23, 2014·2 cites·12 claims
- 0461US8557668B2Method for forming N-shaped bottom stress linerYANG XIAODONG·Filed 2012·Granted Oct 15, 2013·1 cites·12 claims
- 0557US10483172B2Transistor device structures with retrograde wells in CMOS applicationsGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 19, 2019·0 cites·16 claims
- 0657US9099380B2Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting deviceGLOBALFOUNDRIES INC·Filed 2014·Granted Aug 4, 2015·0 cites·20 claims
- 0753US9852954B2Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structuresGLOBALFOUNDRIES INC·Filed 2015·Granted Dec 26, 2017·0 cites·19 claims
- 0853US8669616B2Method for forming N-shaped bottom stress linerGLOBALFOUNDRIES SG PTE LTD·Filed 2013·Granted Mar 11, 2014·0 cites·20 claims
- 0952US9601578B2Non-planar vertical dual source drift metal-oxide semiconductor (VDSMOS)GLOBALFOUNDRIES INC·Filed 2014·Granted Mar 21, 2017·0 cites·11 claims
- 1052US9209181B2Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structuresGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 8, 2015·0 cites·10 claims
- 1149US9362357B2Blanket EPI super steep retrograde well formation without Si recessGLOBALFOUNDRIES INC·Filed 2015·Granted Jun 7, 2016·0 cites·20 claims
- 1245US10796973B2Test structures connected with the lowest metallization levels in an interconnect structureGLOBALFOUNDRIES INC·Filed 2019·Granted Oct 6, 2020·0 cites·17 claims
- 1344US10790204B2Test structure leveraging the lowest metallization level of an interconnect structureGLOBALFOUNDRIES INC·Filed 2018·Granted Sep 29, 2020·0 cites·18 claims
- 1444US2015340501A1Forming independent-gate finfet with tilted pre-amorphization implantation and resulting deviceGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 1542US8664717B2Semiconductor device with an oversized local contact as a Faraday shieldLIU YANXIANG·Filed 2012·Granted Mar 4, 2014·0 cites·23 claims
- 1638US2014070358A1Method of tailoring silicon trench profile for super steep retrograde well field effect transistorQI YI·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →