Inventor · disambiguated record
Fumiyuki Osanai
Also filed as: OSANAI FUMIYUKI
13 granted patents·8 pending applications·114 citations·filing 2005–2024
91Inventor score
Top patents by PatentIndex Score
21 records- 0196US8422263B2Load reduced memory module and memory system including the sameSAITO SHUNICHI·Filed 2010·Granted Apr 16, 2013·40 cites·21 claims
- 0291US7656186B2Calibration circuit, semiconductor device including the same, and data processing systemELPIDA MEMORY INC·Filed 2008·Granted Feb 2, 2010·16 cites·7 claims
- 0389US7994812B2Calibration circuit, semiconductor device including the same, and data processing systemELPIDA MEMORY INC·Filed 2009·Granted Aug 9, 2011·13 cites·13 claims
- 0488US7391113B2Semiconductor deviceELPIDA MEMORY INC·Filed 2006·Granted Jun 24, 2008·14 cites·11 claims
- 0574US9076500B2Memory module including plural memory devices and data register bufferELPIDA MEMORY INC·Filed 2012·Granted Jul 7, 2015·5 cites·17 claims
- 0674US7538431B2Semiconductor deviceELPIDA MEMORY INC·Filed 2008·Granted May 26, 2009·5 cites·13 claims
- 0773US7569428B2Method for manufacturing semiconductor device, semiconductor device and apparatus comprising sameELPIDA MEMORY INC·Filed 2006·Granted Aug 4, 2009·6 cites·17 claims
- 0868US7667317B2Semiconductor package with bypass capacitorELPIDA MEMORY INC·Filed 2007·Granted Feb 23, 2010·4 cites·17 claims
- 0967US7714424B2Stacked-type semiconductor packageELPIDA MEMORY INC·Filed 2008·Granted May 11, 2010·3 cites·1 claims
- 1067US7375422B2Stacked-type semiconductor packageELPIDA MEMORY INC·Filed 2005·Granted May 20, 2008·3 cites·13 claims
- 1164US8395412B2Calibration circuit, semiconductor device including the same, and data processing systemOSANAI FUMIYUKI·Filed 2011·Granted Mar 12, 2013·2 cites·20 claims
- 1261US8362614B2Fine pitch grid array type semiconductor deviceELPIDA MEMORY INC·Filed 2005·Granted Jan 29, 2013·2 cites·11 claims
- 1360US2024421040A1Apparatus including tsv structureMICRON TECHNOLOGY INC·Filed 2024·Application pending·0 cites
- 1457US7847377B2Semiconductor device including semiconductor chip with two pad rowsELPIDA MEMORY INC·Filed 2006·Granted Dec 7, 2010·1 cites·13 claims
- 1550US2013215659A1Load reduced memory module and memory system including the sameELPIDA MEMORY INC·Filed 2013·Application pending·0 cites
- 1646US2009001548A1Semiconductor packageELPIDA MEMORY INC·Filed 2008·Application pending·0 cites
- 1742US2007164435A1Semiconductor deviceELPIDA MEMORY INC·Filed 2006·Application pending·0 cites
- 1838US2010312925A1Load reduced memory moduleELPIDA MEMORY INC·Filed 2010·Application pending·0 cites
- 1938US2010312956A1Load reduced memory moduleELPIDA MEMORY INC·Filed 2010·Application pending·0 cites
- 2036US2013138898A1Memory module including plural memory devices and command address register bufferELPIDA MEMORY INC·Filed 2012·Application pending·0 cites
- 2129US2012250264A1Memory module having memory chip and register bufferOSANAI FUMIYUKI·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →