Load reduced memory module and memory system including the same

Abstract

A device includes a printed circuit board, a clock connector provided on the printed circuit board and configured to be supplied with a first clock signal, a first register buffer provided on the printed circuit board, coupled to the clock connector and, including a first clock generator that produces a second clock signal in response to the first clock signal, a plurality of data connectors, provided on the printed circuit board, a plurality of memory chips each provided on the printed circuit board and including a first data terminal, and a plurality of second register buffers each provided on the printed circuit board independently of the first register buffer.

What is claimed is: 
     
         1 . A device comprising:
 a printed circuit board;   a clock connector provided on the printed circuit board and configured to be supplied with a first clock signal;   a first register buffer provided on the printed circuit board, coupled to the clock connector and including a first clock generator that produces a second clock signal in response to the first clock signal;   a plurality of data connectors provided on the printed circuit board;   a plurality of memory chips each provided on the printed circuit board and including a first data terminal; and   a plurality of second register buffers each provided on the printed circuit board independently of the first register buffer;   wherein each of the second register buffers comprises:
 a clock terminal configured to receive the second crock signal; 
 a second date terminal coupled to the first data terminal of an associated one of the memory chips; 
 a third data terminal coupled to an associated one of the data connectors; 
 a second clock generator configured to produce a third clock signal in response to the second clock signal; and 
 a data transfer circuit coupled between the second and third data terminals and configured to perform a data transfer therebetween in response to the third clock signal. 
   
     
     
         2 . The device as claimed in  claim 1 , wherein the first clock generator include a PLL circuit and the second clock generator of each of the second register buffers includes a DLL circuit. 
     
     
         3 . The device as claimed in  claim 1 , wherein the data transfer circuit of each of the second register buffers includes first and second FIFO circuits that are coupled between the second and third data terminals in parallel to each other. 
     
     
         4 . The device, as claimed in  claim 3 , wherein the first clock generator includes a PLL circuit and the second clock generator of each of the second register buffers includes a DLL circuit. 
     
     
         5 . The device as claimed in  claim 3 , wherein the first FIFO circuit operatively transfers read data from the second data terminal to the third data terminal and the second FIFO circuit operatively transfers write data from the third data terminal to the second data terminal. 
     
     
         6 . The device as claimed in  claim 1 , wherein each of the memory chips includes a first data strobe terminal, each of the second register buffers further comprises a second data strobe terminal coupled to the first data strobe terminal of the associated one of the memory chips and a delay circuit coupled between the second data strobe terminal and the data transfer circuit. 
     
     
         7 . The device as claimed in  claim 6 , wherein the data transfer circuit of each of the second register buffers includes first and second FIFO circuits that are coupled between the second and third data terminals in parallel to each other. 
     
     
         8 . The device as claimed in  claim 6 , wherein the first clock generator includes a PLL circuit and the second clock generator of each of the second register buffers includes a DLL circuit. 
     
     
         9 . The device as claimed in  claim 1 , wherein each of the second register buffers further comprises a control circuit which produces a control signal and the second clock generator of each of the second register buffers is configured to operate in response to the control signal. 
     
     
         10 . The device as claimed in  claim 9 , wherein the data transfer circuit of each of the second register buffers includes first and second FIFO circuits that are coupled between the second and third data terminals in parallel to each other. 
     
     
         11 . The device as claimed in  claim 9 , wherein the first clock generator includes a PLL circuit and the second clock generator of each of the second register buffers includes a DLL circuit. 
     
     
         12 . The device as claimed in  claim 1 , wherein the first clock generator operatively compares a phase of the first clock signal and a phase of the second clock signal to produce a first comparison result and generate the second clock in response to the first comparison result, and the first clock generator operatively compares the phase of the second clock signal and a phase of the third clock signal to produce a second comparison result and generate the second clock in response to the second comparison result. 
     
     
         13 . The device as claimed in  claim 1 , wherein the first, second and third clock signals are substantially in phase with each other. 
     
     
         14 . The device as claimed in  claim 1 , further comprising a plurality of command/address/control connectors provided on the printed circuit board,
 wherein the first register includes a register circuit coupled to the command/address/control connectors.   
     
     
         15 . A device comprising;
 a clock terminal configured to receive a first clock signal;   a first terminal configured to be externally supplied with read data and externally output write data;   a second terminal configured to be externally supplied with the write data and externally output the read data;   a clock generator configured to produce a second clock signal in response to the first clock signal; and   a data transfer circuit coupled between the first and second data terminals and configured to perform a data transfer therebetween in response to the second clock signal.   
     
     
         16 . The device as claimed in  claim 15 , wherein the clock generator includes a DLL circuit. 
     
     
         17 . The device as claimed in  claim 15 , wherein the data transfer circuit includes first and second FIFO circuits that are coupled between the second and third data terminals in parallel to each other. 
     
     
         18 . The device as claimed in  claim 17 , wherein the clock generator includes a DLL circuit. 
     
     
         19 . The device as claimed in  claim 15 , further comprising a data strobe terminal configured to be externally supplied with a strobe signal, and a delay circuit coupled between the first data strobe terminal and the data transfer circuit. 
     
     
         20 . The device as claimed in  claim 19 , wherein the data transfer circuit includes first and second FIFO circuits that are coupled between the first and second data terminals in parallel to each other.