Inventor · disambiguated record
Qiqing C. Ouyang
Also filed as: OUYANG QIQING · OUYANG QIQING C · OUYANG QIQING CHRISTINE
84 granted patents·14 pending applications·2,113 citations·filing 2000–2020
99Inventor score
Top patents by PatentIndex Score
98 records- 0199US8895395B1Reduced resistance SiGe FinFET devices and method of forming sameIBM·Filed 2013·Granted Nov 25, 2014·335 cites·15 claims
- 0299US6943407B2Low leakage heterojunction vertical transistors and high performance devices thereofIBM·Filed 2003·Granted Sep 13, 2005·494 cites·28 claims
- 0398US9643181B1Integrated microfluidics systemIBM·Filed 2016·Granted May 9, 2017·28 cites·20 claims
- 0498US7368358B2Method for producing field effect device that includes epitaxially growing SiGe source/drain regions laterally from a silicon bodyIBM·Filed 2006·Granted May 6, 2008·62 cites·10 claims
- 0598US7057216B2High mobility heterojunction complementary field effect transistors and methods thereofIBM·Filed 2003·Granted Jun 6, 2006·151 cites·18 claims
- 0697US9505611B1Integration of electromechanical and CMOS devices in front-end-of-line using replacement metal gate process flowGLOBALFOUNDRIES INC·Filed 2015·Granted Nov 29, 2016·18 cites·14 claims
- 0797US6319799B1High mobility heterojunction transistor and methodUNIV TEXAS·Filed 2000·Granted Nov 20, 2001·160 cites·30 claims
- 0896US9443873B1Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy stepIBM·Filed 2015·Granted Sep 13, 2016·11 cites·20 claims
- 0996US7309626B2Quasi self-aligned source/drain FinFET processIBM·Filed 2005·Granted Dec 18, 2007·139 cites·11 claims
- 1095US7872303B2FinFET with longitudinal stress in a channelIBM·Filed 2008·Granted Jan 18, 2011·31 cites·14 claims
- 1195US7510904B2Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetectorIBM·Filed 2006·Granted Mar 31, 2009·22 cites·14 claims
- 1295US7205604B2Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereofIBM·Filed 2003·Granted Apr 17, 2007·98 cites·20 claims
- 1394US10176990B2SiGe FinFET with improved junction doping controlIBM·Filed 2016·Granted Jan 8, 2019·7 cites·20 claims
- 1494US9502420B1Structure and method for highly strained germanium channel fins for high mobility pFINFETsIBM·Filed 2015·Granted Nov 22, 2016·10 cites·17 claims
- 1594US8993406B1FinFET device having a merged source drain region under contact areas and unmerged fins between contact areas, and a method of manufacturing sameIBM·Filed 2013·Granted Mar 31, 2015·14 cites·11 claims
- 1693US7227205B2Strained-silicon CMOS device and methodIBM·Filed 2004·Granted Jun 5, 2007·72 cites·5 claims
- 1792US7968915B2Dual stress memorization technique for CMOS applicationIBM·Filed 2009·Granted Jun 28, 2011·17 cites·6 claims
- 1892US7381655B2Mandrel/trim alignment in SIT processingIBM·Filed 2005·Granted Jun 3, 2008·15 cites·6 claims
- 1990US9647119B1Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy stepIBM·Filed 2016·Granted May 9, 2017·4 cites·6 claims
- 2090US7834399B2Dual stress memorization technique for CMOS applicationIBM·Filed 2007·Granted Nov 16, 2010·15 cites·6 claims
- 2190US7547641B2Super hybrid SOI CMOS devicesIBM·Filed 2007·Granted Jun 16, 2009·15 cites·4 claims
- 2290US7161220B2High speed photodiode with a barrier layer for blocking or eliminating slow photonic carriers and method for forming sameIBM·Filed 2006·Granted Jan 9, 2007·11 cites·19 claims
- 2389US9391173B2FinFET device with vertical silicide on recessed source/drain epitaxy regionsIBM·Filed 2014·Granted Jul 12, 2016·7 cites·13 claims
- 2489US9379219B1SiGe finFET with improved junction doping controlIBM·Filed 2016·Granted Jun 28, 2016·4 cites·1 claims
- 2589US7705345B2High performance strained silicon FinFETs device and method for forming sameIBM·Filed 2004·Granted Apr 27, 2010·52 cites·18 claims
- 2689US7525161B2Strained MOS devices using source/drain epitaxyIBM·Filed 2007·Granted Apr 28, 2009·17 cites·9 claims
- 2789US7453113B2Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereofIBM·Filed 2007·Granted Nov 18, 2008·14 cites·1 claims
- 2888US9530699B2Semiconductor device including gate channel having adjusted threshold voltageIBM·Filed 2015·Granted Dec 27, 2016·4 cites·6 claims
- 2988US9502408B2FinFET device including fins having a smaller thickness in a channel region, and a method of manufacturing sameGLOBALFOUNDRIES INC·Filed 2013·Granted Nov 22, 2016·9 cites·10 claims
- 3088US7485537B2Method of fabricating a vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thicknessIBM·Filed 2006·Granted Feb 3, 2009·12 cites·1 claims
- 3187US11493901B2Detection of defect in edge device manufacturing by artificial intelligenceIBM·Filed 2020·Granted Nov 8, 2022·2 cites·17 claims
- 3287US9443963B2SiGe FinFET with improved junction doping controlIBM·Filed 2014·Granted Sep 13, 2016·5 cites·18 claims
- 3386US7911024B2Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereofIBM·Filed 2010·Granted Mar 22, 2011·6 cites·4 claims
- 3486US7808081B2Strained-silicon CMOS device and methodIBM·Filed 2007·Granted Oct 5, 2010·11 cites·1 claims
- 3586US6927414B2High speed lateral heterojunction MISFETs realized by 2-dimensional bandgap engineering and methods thereofIBM·Filed 2003·Granted Aug 9, 2005·45 cites·23 claims
- 3684US7393735B2Structure for and method of fabricating a high-mobility field-effect transistorIBM·Filed 2005·Granted Jul 1, 2008·10 cites·12 claims
- 3784US6855963B1Ultra high-speed Si/SiGe modulation-doped field effect transistors on ultra thin SOI/SGOI substrateIBM·Filed 2003·Granted Feb 15, 2005·25 cites·74 claims
- 3883US9412865B1Reduced resistance short-channel InGaAs planar MOSFETIBM·Filed 2016·Granted Aug 9, 2016·3 cites·1 claims
- 3983US9276118B2FinFET device having a merge source drain region under contact areas and unmerged fins between contact areas, and a method of manufacturing sameGLOBALFOUNDRIES INC·Filed 2015·Granted Mar 1, 2016·3 cites·18 claims
- 4081US9576806B2FinFET device with vertical silicide on recessed source/drain epitaxy regionsIBM·Filed 2016·Granted Feb 21, 2017·2 cites·20 claims
- 4181US7348611B2Strained complementary metal oxide semiconductor (CMOS) on rotated wafers and methods thereofIBM·Filed 2005·Granted Mar 25, 2008·7 cites·16 claims
- 4279US9590106B1Semiconductor device including epitaxially formed buried channel regionIBM·Filed 2016·Granted Mar 7, 2017·2 cites·1 claims
- 4379US8587063B2Hybrid double box back gate silicon-on-insulator wafers with enhanced mobility channelsDENNARD ROBERT H·Filed 2009·Granted Nov 19, 2013·8 cites·24 claims
- 4479US7618857B2Method of reducing detrimental STI-induced stress in MOSFET channelsIBM·Filed 2007·Granted Nov 17, 2009·8 cites·16 claims
- 4579US7294879B2Vertical MOSFET with dual work function materialsIBM·Filed 2003·Granted Nov 13, 2007·21 cites·7 claims
- 4678US7375410B2Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereofIBM·Filed 2004·Granted May 20, 2008·17 cites·14 claims
- 4777US7598147B2Method of forming CMOS with Si:C source/drain by laser melting and recrystallizationIBM·Filed 2007·Granted Oct 6, 2009·5 cites·20 claims
- 4876US7115965B2Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operationIBM·Filed 2004·Granted Oct 3, 2006·16 cites·14 claims
- 4975US7763518B2Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereofIBM·Filed 2008·Granted Jul 27, 2010·4 cites·17 claims
- 5075US7342294B2SOI bipolar transistors with reduced self heatingIBM·Filed 2005·Granted Mar 11, 2008·5 cites·17 claims
Showing the top 50 of 98 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →