Inventor · disambiguated record
David Gerald Farber
Also filed as: FARBER DAVID · FARBER DAVID G · FARBER DAVID GERALD
19 granted patents·5 pending applications·197 citations·filing 2000–2016
93Inventor score
Files withTEXAS INSTRUMENTS INC13GLOBALFOUNDRIES INC2MOTOROLA INC2MOWRY ANTHONY C2FARBER DAVID GERALD1
Top patents by PatentIndex Score
24 records- 0194US7741663B2Air gap spacer formationGLOBALFOUNDRIES INC·Filed 2008·Granted Jun 22, 2010·57 cites·20 claims
- 0290US8064197B2Heat management using power management informationMOWRY ANTHONY C·Filed 2009·Granted Nov 22, 2011·27 cites·21 claims
- 0390US6232134B1Method and apparatus for monitoring wafer characteristics and/or semiconductor processing consistency using wafer charge distribution measurementsMOTOROLA INC·Filed 2000·Granted May 15, 2001·58 cites·40 claims
- 0485US8665592B2Heat management using power management informationMOWRY ANTHONY C·Filed 2011·Granted Mar 4, 2014·8 cites·16 claims
- 0581US6780756B1Etch back of interconnect dielectricsTEXAS INSTRUMENTS INC·Filed 2003·Granted Aug 24, 2004·27 cites·42 claims
- 0677US9490143B1Method of fabricating semiconductorsTEXAS INSTRUMENTS INC·Filed 2015·Granted Nov 8, 2016·2 cites·20 claims
- 0769US9054158B2Method of forming a metal contact opening with a width that is smaller than the minimum feature size of a photolithographically-defined openingTEXAS INSTRUMENTS INC·Filed 2013·Granted Jun 9, 2015·2 cites·20 claims
- 0866US10453700B2Low damage low-k dielectric etchTEXAS INSTRUMENTS INC·Filed 2015·Granted Oct 22, 2019·1 cites·20 claims
- 0964US9437449B2Uniform, damage free nitride etchTEXAS INSTRUMENTS INC·Filed 2013·Granted Sep 6, 2016·1 cites·20 claims
- 1063US7745337B2Method of optimizing sidewall spacer size for silicide proximity with in-situ cleanGLOBALFOUNDRIES INC·Filed 2008·Granted Jun 29, 2010·2 cites·26 claims
- 1161US8507386B2Lateral uniformity in silicon recess etchFARBER DAVID GERALD·Filed 2010·Granted Aug 13, 2013·2 cites·17 claims
- 1258US8564120B2Heat dissipation in temperature critical device areas of semiconductor devices by heat pipes connecting to the substrate backsideMOWRY ANTHONY·Filed 2009·Granted Oct 22, 2013·1 cites·20 claims
- 1354US7687407B2Method for reducing line edge roughness for conductive featuresTEXAS INSTRUMENTS INC·Filed 2005·Granted Mar 30, 2010·2 cites·17 claims
- 1452US9881795B2Method of fabricating semiconductorsTEXAS INSTRUMENTS INC·Filed 2016·Granted Jan 30, 2018·0 cites·15 claims
- 1549US9704720B2Uniform, damage free nitride ETCHTEXAS INSTRUMENTS INC·Filed 2016·Granted Jul 11, 2017·0 cites·20 claims
- 1648US7112288B2Methods for inspection sample preparationTEXAS INSTRUMENTS INC·Filed 2002·Granted Sep 26, 2006·4 cites·12 claims
- 1744US6245686B1Process for forming a semiconductor device and a process for operating an apparatusMOTOROLA INC·Filed 2000·Granted Jun 12, 2001·3 cites·20 claims
- 1843US9224657B2Hard mask for source/drain epitaxy controlTEXAS INSTRUMENTS INC·Filed 2013·Granted Dec 29, 2015·0 cites·19 claims
- 1943US2008268589A1Shallow trench divot control postTEXAS INSTRUMENTS INC·Filed 2007·Application pending·0 cites
- 2043US2009042399A1Method for Dry Develop of Trilayer Photoresist PatternsSMITH BRIAN ASHLEY·Filed 2007·Application pending·0 cites
- 2142US7087518B2Method of passivating and/or removing contaminants on a low-k dielectric/copper surfaceTEXAS INSTRUMENTS INC·Filed 2003·Granted Aug 8, 2006·0 cites·7 claims
- 2242US2015187661A1Dual layer hardmask for embedded epi growthTEXAS INSTRUMENTS INC·Filed 2014·Application pending·0 cites
- 2339US2003170992A1Method of passivating and/or removing contaminants on a low-k dielectric/copper surfaceFiled 2002·Application pending·0 cites
- 2439US2004169279A1Etch back of interconnect dielectricsFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →