Inventor · disambiguated record
Leon Sigal
Also filed as: SIGAL LEON · SIGAL LEON J · SIGAL LEON JACOB
32 granted patents·13 pending applications·312 citations·filing 1990–2023
96Inventor score
Top patents by PatentIndex Score
45 records- 0185US7888959B2Apparatus and method for hardening latches in SOI CMOS devicesIBM·Filed 2007·Granted Feb 15, 2011·11 cites·4 claims
- 0285US5504441ATwo-phase overlapping clocking technique for digital dynamic circuitsIBM·Filed 1994·Granted Apr 2, 1996·43 cites·14 claims
- 0383US8914765B2Power grid generation through modification of an initial power grid based on power grid analysisIBM·Filed 2013·Granted Dec 16, 2014·7 cites·14 claims
- 0482US5493644APolygon span interpolator with main memory Z bufferHEWLETT PACKARD CO·Filed 1991·Granted Feb 20, 1996·99 cites·17 claims
- 0580US5124572AVLSI clocking system using both overlapping and non-overlapping clocksHEWLETT PACKARD CO·Filed 1990·Granted Jun 23, 1992·36 cites·12 claims
- 0674US5543731ADynamic and preset static multiplexer in front of latch circuit for use in static circuitsIBM·Filed 1995·Granted Aug 6, 1996·27 cites·5 claims
- 0771US9104832B1Identifying and mitigating electromigration failures in signal nets of an integrated circuit chip designIBM·Filed 2014·Granted Aug 11, 2015·3 cites·20 claims
- 0870US7100144B2System and method for topology selection to minimize leakage power during synthesisIBM·Filed 2003·Granted Aug 29, 2006·14 cites·34 claims
- 0969US12500144B2Backside self aligned skip viaIBM·Filed 2023·Granted Dec 16, 2025·0 cites·20 claims
- 1069US12451412B2Backside gate via structure using self-aligned schemeIBM·Filed 2023·Granted Oct 21, 2025·0 cites·20 claims
- 1164US9552455B2Method for an efficient modeling of the impact of device-level self-heating on electromigration limited current specificationsGLOBALFOUNDRIES INC·Filed 2015·Granted Jan 24, 2017·1 cites·15 claims
- 1264US8117579B2LSSD compatibility for GSD unified global clock buffersWARNOCK JAMES DOUGLAS·Filed 2008·Granted Feb 14, 2012·6 cites·13 claims
- 1364US7568173B2Independent migration of hierarchical designs with methods of finding and fixing opens during migrationIBM·Filed 2007·Granted Jul 28, 2009·3 cites·12 claims
- 1462US5910730ADigital circuit noise margin improvementIBM·Filed 1996·Granted Jun 8, 1999·17 cites·24 claims
- 1559US12271674B2Generating a power delivery network based on the routing of signal wires within a circuit designIBM·Filed 2022·Granted Apr 8, 2025·0 cites·17 claims
- 1659US11916384B2Region-based power grid generation through modification of an initial power grid based on timing analysisIBM·Filed 2021·Granted Feb 27, 2024·0 cites·20 claims
- 1758US12381149B2Cell optimization through source resistance improvementIBM·Filed 2022·Granted Aug 5, 2025·0 cites·14 claims
- 1858US2024429098A1Merged self-aligned backside contactIBM·Filed 2023·Application pending·0 cites
- 1958US2025194149A1Contact extension for additional wiring pathsIBM·Filed 2023·Application pending·0 cites
- 2057US11822867B2Hierarchical color decomposition of process layers with shape and orientation requirementsIBM·Filed 2021·Granted Nov 21, 2023·0 cites·20 claims
- 2157US2025191995A1Thermal transfer vias and semiconductor via structure for enhanced thermal transferIBM·Filed 2023·Application pending·0 cites
- 2257US2024371728A1Backside contacts for source/drain regionsIBM·Filed 2023·Application pending·0 cites
- 2357US2025040240A1Stacked field effect transistor hybrid gate cutIBM·Filed 2023·Application pending·0 cites
- 2456US12112114B2Hierarchical color decomposition of library cells with boundary-aware color selectionIBM·Filed 2021·Granted Oct 8, 2024·0 cites·20 claims
- 2556US2024203792A1Self-aligned backside gate contactsIBM·Filed 2022·Application pending·0 cites
- 2655US12176289B2Semiconductor device design mitigating latch-upIBM·Filed 2022·Granted Dec 24, 2024·0 cites·20 claims
- 2755US11663391B2Latch-up avoidance for sea-of-gatesIBM·Filed 2021·Granted May 30, 2023·0 cites·17 claims
- 2855US2025169050A1Second-level metallization testable fully integrated and multi-functional static random access memory and scannable latchesIBM·Filed 2023·Application pending·0 cites
- 2954US2024162118A1Backside skip-level through via for backside signal line connectionIBM·Filed 2022·Application pending·0 cites
- 3053US2024170532A1Shared source/drain contact for stacked field-effect transistorIBM·Filed 2022·Application pending·0 cites
- 3153US2024162895A1Competing path ring-oscillator for direct measurement of a latch timing window parametersIBM·Filed 2022·Application pending·0 cites
- 3252US2024220696A1Cell-based signal connectivity between wafer frontside and backsideIBM·Filed 2022·Application pending·0 cites
- 3351US7589565B2Low-power multi-output local clock bufferIBM·Filed 2008·Granted Sep 15, 2009·0 cites·20 claims
- 3450US7456671B2Hierarchical scalable high resolution digital programmable delay circuitIBM·Filed 2007·Granted Nov 25, 2008·1 cites·22 claims
- 3550US6629298B1Automated programmable process and method for the improvement of electrical digital signal transition rates in a VLSI designIBM·Filed 1999·Granted Sep 30, 2003·24 cites·16 claims
- 3649US11106850B2Flexible constraint-based logic cell placementIBM·Filed 2019·Granted Aug 31, 2021·0 cites·20 claims
- 3749US2025005252A1Yielding and routable circuit co-design using viabarsIBM·Filed 2023·Application pending·0 cites
- 3848US11074391B2Characterizing and simulating library gates to enable identification and elimination of electromigration violations in semiconductor chipsIBM·Filed 2019·Granted Jul 27, 2021·0 cites·9 claims
- 3946US8354858B2Apparatus and method for hardening latches in SOI CMOS devicesIBM·Filed 2011·Granted Jan 15, 2013·0 cites·9 claims
- 4043US2004143613A1Floating point bypass register to resolve data dependencies in pipelined instruction sequencesIBM·Filed 2004·Application pending·0 cites
- 4141US9990454B2Early analysis and mitigation of self-heating in design flowsIBM·Filed 2016·Granted Jun 5, 2018·0 cites·20 claims
- 4239US5757682AParallel calculation of exponent and sticky bit during normalizationIBM·Filed 1995·Granted May 26, 1998·7 cites·7 claims
- 4337US5627774AParallel calculation of exponent and sticky bit during normalizationIBM·Filed 1995·Granted May 6, 1997·6 cites·11 claims
- 4435US5742535AParallel calculation of exponent and sticky bit during normalizationIBM·Filed 1995·Granted Apr 21, 1998·5 cites·19 claims
- 4531US5742536AParallel calculation of exponent and sticky bit during normalizationIBM·Filed 1995·Granted Apr 21, 1998·2 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →