Inventor · disambiguated record
Devendra Natekar
Also filed as: NATEKAR DEVENDRA
14 granted patents·6 pending applications·495 citations·filing 2001–2013
93Inventor score
Top patents by PatentIndex Score
20 records- 0198US7402515B2Method of forming through-silicon vias with stress buffer collars and resulting devicesINTEL CORP·Filed 2005·Granted Jul 22, 2008·375 cites·22 claims
- 0291US7443030B2Thin silicon based substrateINTEL CORP·Filed 2006·Granted Oct 28, 2008·18 cites·10 claims
- 0389US7528006B2Integrated circuit die containing particle-filled through-silicon metal vias with reduced thermal expansionINTEL CORP·Filed 2005·Granted May 5, 2009·17 cites·12 claims
- 0486US7144299B2Methods and devices for supporting substrates using fluidsINTEL CORP·Filed 2005·Granted Dec 5, 2006·13 cites·13 claims
- 0582US7514116B2Horizontal Carbon Nanotubes by Vertical Growth and RollingINTEL CORP·Filed 2005·Granted Apr 7, 2009·9 cites·14 claims
- 0681US7915081B2Flexible interconnect pattern on semiconductor packageINTEL CORP·Filed 2006·Granted Mar 29, 2011·9 cites·11 claims
- 0775US7589424B2Thin silicon based substrateINTEL CORP·Filed 2008·Granted Sep 15, 2009·5 cites·10 claims
- 0873US7413995B2Etched interposer for integrated circuit devicesINTEL CORP·Filed 2004·Granted Aug 19, 2008·17 cites·10 claims
- 0971US7592704B2Etched interposer for integrated circuit devicesINTEL CORP·Filed 2008·Granted Sep 22, 2009·4 cites·19 claims
- 1071US7049208B2Method of manufacturing of thin based substrateINTEL CORP·Filed 2004·Granted May 23, 2006·13 cites·8 claims
- 1170US8409924B2Flexible interconnect pattern on semiconductor packageTOMITA YOSHIHIRO·Filed 2012·Granted Apr 2, 2013·2 cites·12 claims
- 1262US8227907B2Flexible interconnect pattern on semiconductor packageTOMITA YOSHIHIRO·Filed 2011·Granted Jul 24, 2012·1 cites·15 claims
- 1359US6803653B1Apparatus for suppressing packaged semiconductor chip curvature while minimizing thermal impedance and maximizing speed/reliabilityADVANCED MICRO DEVICES INC·Filed 2001·Granted Oct 12, 2004·12 cites·10 claims
- 1451US8518750B2Flexible interconnect pattern on semiconductor packageTOMITA YOSHIHIRO·Filed 2013·Granted Aug 27, 2013·0 cites·6 claims
- 1551US2009072013A1Nano-scale particle paste for wiring microelectronic devices using ink-jet printingNATEKAR DEVENDRA·Filed 2008·Application pending·0 cites
- 1645US2010193952A1Integrated circuit die containing particale-filled through-silicon metal vias with reduced thermal expansionARANA LEONEL·Filed 2009·Application pending·0 cites
- 1744US2008251932A1Method of forming through-silicon vias with stress buffer collars and resulting devicesARANA LEONEL R·Filed 2008·Application pending·0 cites
- 1838US2007000592A1Apparatus and method to operate on one or more attach sites in die package assemblyINTEL CORP·Filed 2005·Application pending·0 cites
- 1937US2006046433A1Thinning semiconductor wafersSTERRETT TERRY L·Filed 2004·Application pending·0 cites
- 2033US2007090517A1Stacked die package with thermally conductive block embedded in substrateMOON SUNG-WON·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →