Inventor · disambiguated record
Jae-Eon Park
Also filed as: PARK JAE-EON
10 granted patents·3 pending applications·68 citations·filing 2005–2022
86Inventor score
Files withSAMSUNG ELECTRONICS CO LTD6ENTEGRIS INC4CHARTERED SEMICONDUCTOR MFG1PARK JAE-EON1SUN MIN-CHUL1
Top patents by PatentIndex Score
13 records- 0194US7297584B2Methods of fabricating semiconductor devices having a dual stress linerSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Nov 20, 2007·34 cites·12 claims
- 0290US7534678B2Methods of forming CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein and circuits formed therebySAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted May 19, 2009·20 cites·20 claims
- 0374US7323419B2Method of fabricating semiconductor deviceSAMSUNG ELECTRONICS CO LTD·Filed 2006·Granted Jan 29, 2008·4 cites·21 claims
- 0471US7800134B2CMOS integrated circuit devices having stressed NMOS and PMOS channel regions thereinSAMSUNG ELECTRONICS CO LTD·Filed 2009·Granted Sep 21, 2010·4 cites·7 claims
- 0569US12037681B2Method for forming carbon rich silicon-containing filmsENTEGRIS INC·Filed 2022·Granted Jul 16, 2024·0 cites·17 claims
- 0668US7838390B2Methods of forming integrated circuit devices having ion-cured electrically insulating layers thereinSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Nov 23, 2010·4 cites·7 claims
- 0766US7541288B2Methods of forming integrated circuit structures using insulator deposition and insulator gap filling techniquesSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Jun 2, 2009·2 cites·23 claims
- 0861US12264392B2Silicon precursor compounds and method for forming silicon-containing filmsENTEGRIS INC·Filed 2021·Granted Apr 1, 2025·0 cites·11 claims
- 0961US11414750B2Method for forming carbon rich silicon-containing filmsENTEGRIS INC·Filed 2020·Granted Aug 16, 2022·0 cites·12 claims
- 1060US12071688B2Precursors and methods for preparing silicon-containing filmsENTEGRIS INC·Filed 2021·Granted Aug 27, 2024·0 cites·15 claims
- 1151US2008029823A1Semiconductor Device Having a Dual Stress Liner and Light Exposure Apparatus for Forming the Dual Stress LinerCHARTERED SEMICONDUCTOR MFG·Filed 2007·Application pending·0 cites
- 1245US2010029072A1Methods of Forming Electrical Interconnects Using Thin Electrically Insulating Liners in Contact HolesPARK JAE-EON·Filed 2009·Application pending·0 cites
- 1342US2008124859A1Methods of Forming CMOS Integrated Circuits Using Gate Sidewall Spacer Reduction TechniquesSUN MIN CHUL·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →