Inventor · disambiguated record
Lee-Lean Shu
Also filed as: SHU LEE-LEAN
47 granted patents·5 pending applications·1,049 citations·filing 1985–2025
99Inventor score
Files withGSI TECHNOLOGY INC38ADVANCED MICRO DEVICES INC3SHU LEE LEAN3SONY ELECTRONICS INC3GIGA SEMICONDUCTOR INC2
Top patents by PatentIndex Score
52 records- 0199US10854284B1Computational memory cell and processing array device with ratioless write portGSI TECHNOLOGY INC·Filed 2020·Granted Dec 1, 2020·16 cites·18 claims
- 0298US10943648B1Ultra low VDD memory cell with ratioless write portGSI TECHNOLOGY INC·Filed 2020·Granted Mar 9, 2021·9 cites·8 claims
- 0398US10930341B1Processing array device that performs one cycle full adder operation and bit line read/write logic featuresGSI TECHNOLOGY INC·Filed 2020·Granted Feb 23, 2021·11 cites·7 claims
- 0498US10535381B2Systems and methods of pipelined output latching involving synchronous memory arraysGSI TECHNOLOGY INC·Filed 2018·Granted Jan 14, 2020·23 cites·20 claims
- 0598US10521229B2Computational memory cell and processing array device using memory cellsGSI TECHNOLOGY INC·Filed 2017·Granted Dec 31, 2019·26 cites·11 claims
- 0698US10249362B2Computational memory cell and processing array device using the memory cells for XOR and XNOR computationsGSI TECHNOLOGY INC·Filed 2017·Granted Apr 2, 2019·33 cites·36 claims
- 0798US9356611B1Systems and methods involving phase detection with adaptive locking/detection featuresGSI TECHNOLOGY INC·Filed 2015·Granted May 31, 2016·31 cites·26 claims
- 0898US9053768B2Systems and methods of pipelined output latching involving synchronous memory arraysGSI TECHNOLOGY INC·Filed 2014·Granted Jun 9, 2015·33 cites·20 claims
- 0998US9018992B1Systems and methods involving phase detection with adaptive locking/detection featuresGSI TECHNOLOGY INC·Filed 2014·Granted Apr 28, 2015·25 cites·51 claims
- 1098US8575982B1Systems and methods including features of power supply noise reduction and/or power-saving for high speed delay linesGSI TECHNOLOGY INC·Filed 2013·Granted Nov 5, 2013·26 cites·21 claims
- 1198US5457407ABinary weighted reference circuit for a variable impedance output bufferSONY ELECTRONICS INC·Filed 1994·Granted Oct 10, 1995·204 cites·8 claims
- 1297US9966118B2Systems and methods of pipelined output latching involving synchronous memory arraysGSI TECHNOLOGY INC·Filed 2016·Granted May 8, 2018·23 cites·20 claims
- 1397US9847111B2Systems and methods of pipelined output latching involving synchronous memory arraysGSI TECHNOLOGY INC·Filed 2016·Granted Dec 19, 2017·23 cites·10 claims
- 1497US9412440B1Systems and methods of pipelined output latching involving synchronous memory arraysGSI TECHNOLOGY INC·Filed 2015·Granted Aug 9, 2016·23 cites·20 claims
- 1596US10877731B1Processing array device that performs one cycle full adder operation and bit line read/write logic featuresGSI TECHNOLOGY INC·Filed 2019·Granted Dec 29, 2020·20 cites·27 claims
- 1696US10192592B2Systems and methods involving data bus inversion memory circuitry, configuration and/or operation including data signals grouped into 10 bits and/or other featuresGSI TECHNOLOGY INC·Filed 2016·Granted Jan 29, 2019·24 cites·29 claims
- 1796US9613670B2Memory systems and methods involving high speed local address circuitryGSI TECHNOLOGY INC·Filed 2016·Granted Apr 4, 2017·23 cites·27 claims
- 1896US9385032B2Systems and methods involving data bus inversion memory circuitry, configuration and/or operationGSI TECHNOLOGY INC·Filed 2014·Granted Jul 5, 2016·26 cites·23 claims
- 1996US9318174B1Memory systems and methods involving high speed local address circuitryGSI TECHNOLOGY INC·Filed 2014·Granted Apr 19, 2016·23 cites·24 claims
- 2096US8400200B1Systems and methods including features of power supply noise reduction and/or power-saving for high speed delay linesKIM JAE HYEONG·Filed 2011·Granted Mar 19, 2013·27 cites·20 claims
- 2195US9613684B2Systems and methods involving propagating read and write address and data through multi-bank memory circuitryGSI TECHNOLOGY INC·Filed 2015·Granted Apr 4, 2017·26 cites·20 claims
- 2295US9384822B2Systems and methods involving data bus inversion memory circuitry, configuration and/or operation including data signals grouped into 10 bits and/or other featuresGSI TECHNOLOGY INC·Filed 2014·Granted Jul 5, 2016·25 cites·20 claims
- 2395US9135986B2Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other featuresGSI TECHNOLOGY INC·Filed 2013·Granted Sep 15, 2015·25 cites·56 claims
- 2494US10725777B2Computational memory cell and processing array device using memory cellsGSI TECHNOLOGY INC·Filed 2017·Granted Jul 28, 2020·12 cites·19 claims
- 2593US8885439B1Systems and methods including clock features such as minimization of simultaneous switching outputs (SSO) effects involving echo clocksGSI TECHNOLOGY INC·Filed 2013·Granted Nov 11, 2014·24 cites·50 claims
- 2691US10958272B2Computational memory cell and processing array device using complementary exclusive or memory cellsGSI TECHNOLOGY INC·Filed 2019·Granted Mar 23, 2021·7 cites·30 claims
- 2791US8488408B1Systems and methods including clock features such as minimization of simultaneous switching outputs (SSO) effects involving echo clocksSHU LEE-LEAN·Filed 2011·Granted Jul 16, 2013·24 cites·20 claims
- 2889US4694205AMidpoint sense amplification scheme for a CMOS DRAMADVANCED MICRO DEVICES INC·Filed 1985·Granted Sep 15, 1987·60 cites·17 claims
- 2988US10303629B2Systems and methods involving data bus inversion memory circuitry, configuration(s) and/or operationGSI TECHNOLOGY INC·Filed 2016·Granted May 28, 2019·5 cites·39 claims
- 3088US4634894ALow power CMOS reference generator with low impedance driverADVANCED MICRO DEVICES INC·Filed 1985·Granted Jan 6, 1987·39 cites·36 claims
- 3185US7292490B1System and method for refreshing a DRAM deviceGSI TECHNOLOGY INC·Filed 2005·Granted Nov 6, 2007·15 cites·24 claims
- 3284US8638144B1Systems and methods involving phase detection with adaptive locking/detection featuresSHYU JYN-BANG·Filed 2010·Granted Jan 28, 2014·7 cites·65 claims
- 3381US10720205B2Systems and methods involving multi-bank, dual-pipe memory circuitryGSI TECHNOLOGY INC·Filed 2015·Granted Jul 21, 2020·6 cites·30 claims
- 3480US4670861ACMOS N-well bias generator and gating systemADVANCED MICRO DEVICES INC·Filed 1985·Granted Jun 2, 1987·45 cites·11 claims
- 3573US10998040B2Computational memory cell and processing array device using the memory cells for XOR and XNOR computationsGSI TECHNOLOGY INC·Filed 2017·Granted May 4, 2021·2 cites·18 claims
- 3673US5519712ACurrent mode test circuit for SRAMSONY ELECTRONICS INC·Filed 1994·Granted May 21, 1996·33 cites·6 claims
- 3767US11227653B1Storage array circuits and methods for computational memory cellsGSI TECHNOLOGY INC·Filed 2018·Granted Jan 18, 2022·3 cites·32 claims
- 3867US11150903B2Computational memory cell and processing array device using memory cellsGSI TECHNOLOGY INC·Filed 2020·Granted Oct 19, 2021·0 cites·8 claims
- 3966US11763881B2Computational memory cell and processing array device using the memory cells for XOR and XNOR computationsGSI TECHNOLOGY INC·Filed 2021·Granted Sep 19, 2023·0 cites·22 claims
- 4066US10860318B2Computational memory cell and processing array device using memory cellsGSI TECHNOLOGY INC·Filed 2017·Granted Dec 8, 2020·1 cites·28 claims
- 4164US2025081474A1Associate processing tightly coupled to high bandwidth memoryGSI TECHNOLOGY INC·Filed 2024·Application pending·0 cites
- 4263US2025349358A1Associative processing cell with xnor+xor functionsGSI TECHNOLOGY INC·Filed 2025·Application pending·0 cites
- 4362US2025348553A1Single cycle binary matrix multiplicationGSI TECHNOLOGY INC·Filed 2025·Application pending·0 cites
- 4461US11194548B2Processing array device that performs one cycle full adder operation and bit line read/write logic featuresGSI TECHNOLOGY INC·Filed 2020·Granted Dec 7, 2021·0 cites·12 claims
- 4561US5355343AStatic random access memory with self timed bit line equalizationSHU LEE LEAN·Filed 1992·Granted Oct 11, 1994·22 cites·8 claims
- 4651US8116161B2System and method for refreshing a DRAM deviceSHU LEE-LEAN·Filed 2007·Granted Feb 14, 2012·2 cites·25 claims
- 4749US2016005458A1Systems and Methods of Sectioned Bit Line Memory Arrays, Including Hierarchical and/or Other FeaturesGSI TECHNOLOGY INC·Filed 2015·Application pending·0 cites
- 4845US6762973B2Data coherent logic for an SRAM deviceGIGA SEMICONDUCTOR INC·Filed 2002·Granted Jul 13, 2004·5 cites·19 claims
- 4943US5384503ASRAM with current-mode read data pathFiled 1992·Granted Jan 24, 1995·8 cites·9 claims
- 5039US2022300255A1Ram true random number generatorGSI TECHNOLOGY INC·Filed 2022·Application pending·0 cites
Showing the top 50 of 52 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →