Systems and Methods of Sectioned Bit Line Memory Arrays, Including Hierarchical and/or Other Features

Abstract

A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. Further, in some embodiments, the sectioned bit lines are arranged in hierarchical arrays. In other implementations, SRAM memory devices may be configured involving sectioned bit lines (including hierarchical) and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.

1 . An SRAM memory device comprising:
 a local section bit line including:
 a plurality of sectioned bit lines (SBLs), each comprising:
 a local bit line; 
 one or more memory cells connected to the local bit line; 
 a local complement bit line connected to the memory cell; & 
 a pass gate coupled to the local bit line; 
 
 a local sense amplifier; 
 a local shared data driver; 
 a global bit line; 
   wherein the local sense amplifier is configured to amplify a signal on a local sense line and provide an output to the global bit line.   
     
     
         2 . The device of  claim 1  wherein the pass gates are configured to connect and/or isolate the sectioned bit line and local sense line. 
     
     
         3 . A local section bit line (LSBL) of an SRAM including:
 a plurality of sectioned bit lines (SBLs), each comprising:
 a local bit line; 
 one or more memory cells connected to the local bit line; 
 a local complement bit line connected to the memory cell; and 
 a pass gate coupled to the local bit line; 
   a local shared sense amplifier;   a local shared data driver;   a global bit line;   wherein the local sense amplifier is configured to amplify a signal on a local sense line and provide an output to the global bit line.   
     
     
         4 . The device of  claim 3  wherein the pass gates are configured to connect and isolate the sectioned bit line and local sense line. 
     
     
         5 . The device of  claim 1  or the invention of any claim herein wherein the one or more memory cells comprise:
 2 or more LSBLs arranged in direction along the bit line (Y direction). 
 
     
     
         6 . The device of  claim 1 ,  claim 5  or the invention of any claim herein wherein the one or more memory cells comprise:
 at least one LSBL arranged in a direction of a word line (X direction). 
 
     
     
         7 . The device of  claim 1  or the invention of any claim herein further comprising at least one local sense amplifier and/or at least one local data driver. 
     
     
         8 . The device of  claim 1  or the invention of any claim herein wherein at least two or more local sense amplifiers and/or at least two or more local data drivers are configured for selection by X and Y addresses. 
     
     
         9 . The device of  claim 1  or the invention of any claim herein, further comprising a global data line. 
     
     
         10 . The device of  claim 1  or the invention of any claim herein, wherein the global bit line is configured to be used as a global data line. 
     
     
         11 . The device of  claim 1  or the invention of any claim herein further comprising multiple level column decoding circuit on the global bit line. 
     
     
         12 . The device of  claim 11  wherein the global bit line is arranged in a same direction as the local bit line(s). 
     
     
         13 . The device of  claim 1  or the invention of any claim herein further comprising at least one multiple level sense amplifiers coupled with one or more of the global bit lines and/or the sectioned bit lines. 
     
     
         14 . The device of  claim 1  or the invention of any claim herein further comprising at least one multiple level data driver coupled with one or more of the global bit lines and/or the sectioned bit lines. 
     
     
         15 . The device of  claim 1  or the invention of any claim herein further comprising a single global bit line sense amplifier for one or more of the local section bit lines (LSBLs). 
     
     
         16 . The device of  claim 1  or the invention of any claim herein further comprising a single global data driver for one or more of the local sectioned bit lines (LSBLs). 
     
     
         17 . The device of  claim 1  or the invention of any claim herein wherein the global bit lines, local sense amplifier enable lines, and local data driver enable lines (signals) on memory cells layout are arranged in a same direction as the local bit lines. 
     
     
         18 . The device of  claim 1  or the invention of any claim herein further comprising a local sense amplifier enable line and/or a local data driver enable line configured as part of Y (column) decoding of the global bit line. 
     
     
         19 . The device of  claim 1  or the invention of any claim herein further comprising local select (LS) lines configured and/or connected as a function of X decoding. 
     
     
         20 . The device of  claim 1  or the invention of any claim herein further comprising one or more local select (LS) lines and/or one or more local pass gate enable lines (Rpb and Wp) configured in a word line direction. 
     
     
         21 . An SRAM memory device comprising:
 a local section bit line including:
 a plurality of sectioned bit lines (SBLs), each comprising:
 a local bit line; 
 one or more memory cells connected to the local bit line; 
 a local complement bit line connected to the memory cell; & 
 a pass gate coupled to the local bit line; 
 
 a local shared sense amplifier; 
 a local shared data driver; 
 a global bit line; and 
   a dummy global bit line that is arranged along or in a comparable path of the global bit line;   wherein the local sense amplifier is configured to amplify a signal on a local sense line and provide an output to the global bit line.   
     
     
         22 . The device of  claim 21  wherein the pass gates are configured to connect and/or isolate the sectioned bit line and local sense line. 
     
     
         23 . The device of  claim 21  or the invention of any claim herein further configured to utilize the dummy global bit line to emulate delay on the global bit line for better timing tracking. 
     
     
         24 . The invention of  claim 23  wherein the timing tracking that is improved includes timing tracking between at least one of the local sense amplifiers and at least one of the global sense amplifiers. 
     
     
         25 . The invention of  claim 21  further comprising circuitry configured to:
 access a plurality of sectioned bit lines, the sectioned bit lines being sections of a global bit line, each sectioned bit line comprising a bit line, one or more memory cells connected to the bit line, a complement bit line connected to the memory cell, and a pass gate coupled to the bit line, wherein a dummy global bit line is arranged along or in a comparable path of the global bit line; 
 pass data/signals to or from memory cells within the sectioned bit line via the pass gates, wherein the pass gates are configured to connect and isolate the sectioned bit lines and the global bit line; 
 determine an estimated delay on the global bit line via measurement of emulated delay information on the dummy global bit line; and 
 utilize the estimated delay and/or the emulated delay information to improve timing tracking. 
 
     
     
         26 . A method of SRAM operation comprising:
 accessing a plurality of sectioned bit lines, the sectioned bit lines being sections of a global bit line, each sectioned bit line comprising a bit line, one or more memory cells connected to the bit line, a complement bit line connected to the memory cell, and a pass gate coupled to the bit line, wherein a dummy global bit line is arranged along or in a comparable path of the global bit line;   passing data/signals to or from memory cells within the sectioned bit line via the pass gates, wherein the pass gates are configured to connect and isolate the sectioned bit lines and the global bit line;   determining an estimated delay on the global bit line via measurement of emulated delay information on the dummy global bit line; and   utilizing the estimated delay and/or the emulated delay information to improve timing tracking.   
     
     
         27 . The method of  claim 26  wherein the timing tracking that is improved includes timing tracking between at least one of the local sense amplifiers and at least one of the global sense amplifiers. 
     
     
         28 . The invention of any claim herein wherein at least one of the global bit line are formed on one or more layers above the memory cell and/or on one or more layers below the memory cell. 
     
     
         29 . The invention of any claim herein, wherein at least one of the control signal lines are formed on one or more layers above the memory cell and/or on one or more layers below the memory cell. 
     
     
         30 . A method of SRAM operation comprising:
 accessing a plurality of sectioned bit lines in a hierarchical memory array, the sectioned bit lines being sections of a global bit line, each sectioned bit line comprising a bit line, one or more memory cells connected to the bit line, a complement bit line connected to the memory cell, and a pass gate coupled to the bit line;   passing data/signals to or from memory cells within the sectioned bit line via the pass gates, wherein the pass gates are configured to connect and isolate the sectioned bit lines and the global bit line.   
     
     
         31 . A method of SRAM operation comprising:
 reading/writing data to one or more of a plurality of sectioned bit lines in a hierarchical memory array, consistent with any claim, configuration and/or aspect of the disclosure herein.   
     
     
         32 . A method of operating a local section bit line (LSBL) of an SRAM comprising:
 accessing a plurality of sectioned bit lines arranged in a hierarchical memory array, the sectioned bit lines being sections of a global bit line, each sectioned bit line comprising a bit line, one or more memory cells connected to the bit line, a complement bit line connected to the memory cell, and a pass gate coupled to the bit line; and   operating the pass gates to connect and/or isolate the sectioned bit lines and the global bit lines.   
     
     
         33 . The method of  claim 32  or the invention of any claim herein, wherein the one or more memory cells comprise two or more LSBLs arranged in direction along the bit line (Y direction). 
     
     
         34 . The method of  claim 32  or the invention of any claim herein, wherein the one or more memory cells comprise at least one LSBL arranged in a direction of a word line (X direction). 
     
     
         35 . The method of  claim 32  or the invention of any claim herein, further comprising:
 operating at least one local sense amplifier and/or at least one local data driver for selection by X and Y addresses. 
 
     
     
         36 . The method of  claim 32  or the invention of any claim herein, further comprising:
 decoding multiple level columns on the global bit line. 
 
     
     
         37 . The method of  claim 32  or the invention of any claim herein, further comprising:
 performing read/write operations using the global bit line, wherein the global bit line is arranged in a same direction as the local bit line(s). 
 
     
     
         38 . The method of  claim 32  or the invention of any claim herein, further comprising:
 amplifying a signal on the local sense line using at least one multiple level sense amplifier, wherein the at least one multiple level sense amplifier is coupled to at least one global bit line and/or the sectioned bit lines. 
 
     
     
         39 . The method of  claim 32  or the invention of any claim herein, further comprising:
 driving data via a multiple level data driver, wherein the multiple level data driver is coupled to at least one global bit line and/or the sectioned bit lines. 
 
     
     
         40 . The method of  claim 32  or the invention of any claim herein, further comprising:
 amplifying a signal on the global bit line via a single global bit line sense amplifier, wherein the single global bit line sense amplifier is coupled to one or more of the local section bit lines (LSBLs). 
 
     
     
         41 . The method of  claim 32  or the invention of any claim herein, wherein the global bit lines, local sense amplifier enable lines, and/or local data driver enable lines are arranged on memory cells in a same direction as the local bit lines. 
     
     
         42 . The method of  claim 32  or the invention of any claim herein, wherein a local sense amplifier enable line and/or a local data driver enable line are arranged as Y direction decoding of the global bit line. 
     
     
         43 . The method of  claim 32  or the invention of any claim herein, further comprising:
 selecting memory cells via local select (LS) lines, wherein the LS lines are configured as a function of X direction decoding. 
 
     
     
         44 . The method of  claim 32  or the invention of any claim herein, wherein one or more local select (LS) lines and/or one or more local pass gate enable lines are configured in a word line direction. 
     
     
         45 . A method of SRAM operation comprising the steps of:
 accessing a plurality of sectioned bit lines arranged in a hierarchical memory array, the sectioned bit lines being sections of a global bit line, each sectioned bit line comprising a bit line, one or more memory cells connected to the bit line, a complement bit line connected to the memory cell, and a pass gate coupled to the bit line;   passing data/signals to or from memory cells within the sectioned bit line via the pass gates; and   operating the pass gates to connect and/or isolate the sectioned bit lines and the global bit lines.   
     
     
         46 . The method of  claim 45  or the invention of any claim herein further comprising emulating delay of the global bit line via a dummy global bit line, wherein the dummy global bit line is arranged along or in a comparable path of the global bit line. 
     
     
         47 . The method of  claim 45  or the invention of any claim herein, wherein delay is emulated for better timing tracking. 
     
     
         48 . The method of  claim 45  or the invention of any claim herein, further comprising:
 determining an estimated delay on a global bit line via measurement of emulated delay information on the dummy global bit line. 
 
     
     
         49 . The method of  claim 45  or the invention of any claim herein, further comprising:
 performing read/write operations using the global bit lines, wherein at least one of the global bit lines is formed in/on one or more layers above the memory cell and/or on one or more layers below the memory cell. 
 
     
     
         50 . The method of  claim 45  or the invention of any claim herein, further comprising:
 controlling operation of the SRAM via the control signal lines, wherein at least one of the control signal lines is formed on one or more layers above the memory cell and/or on one or more layers below the memory cell. 
 
     
     
         51 . An SRAM memory device comprising:
 a global bit line;   a sectioned bit line (SBL) comprising:
 a local bit line; 
 one or more memory cells connected to the local bit line; 
 a local complement bit line connected to the memory cell; and 
 a pass gate coupled to the local bit line; 
   wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.   
     
     
         52 . The device of  claim 1 ,  claim 51  or the invention of any claim herein, wherein a drain of the pass gate is coupled to the local bit line. 
     
     
         53 . The device of  claim 1 ,  claim 51  or the invention of any claim herein further comprising a plurality of sectioned bit lines configured along a direction parallel to local bit lines associated with the plurality of sectioned bit lines. 
     
     
         54 . The device of  claim 1 ,  claim 51  or the invention of any claim herein further comprising a plurality of sectioned bit lines configured along a direction parallel to word lines associated with the plurality of sectioned bit lines. 
     
     
         55 . The device of  claim 1 ,  claim 51  or the invention of any claim herein further comprising first modules of sectioned bit lines (SBLs) configured along a direction parallel to local bit lines associated with the sectioned bit lines, and second modules of SBLs configured along a direction parallel to word lines associated with the sectioned bit lines. 
     
     
         56 . The device of  claim 1 ,  claim 51  or the invention of any claim herein, wherein the global bit line and local bit line are oriented in a same direction. 
     
     
         57 . The device of  claim 1 ,  claim 51  or the invention of any claim herein, further comprising a plurality of local section lines;
 wherein the global bit line has an orientation that is orthogonal to an orientation of the local section lines. 
 
     
     
         58 . The device of  claim 1 ,  claim 51 ,  claim 57  or the invention of any claim herein, wherein an SBL connects to each of the plurality of local section lines. 
     
     
         59 . The device of  claim 1 ,  claim 51  or the invention of any claim herein wherein the pass gate is a write pass gate defining a write path. 
     
     
         60 . The device of  claim 59  wherein the write pass gate is an NMOS device. 
     
     
         61 . The device of  claim 1 ,  claim 51  or the invention of any claim herein further comprising a read pass gate defining a read path. 
     
     
         62 . The device of  claim 61  wherein the read pass gate is an PMOS device. 
     
     
         63 . The device of  claim 1 ,  claim 51  or the invention of any claim herein, wherein the local bit line is formed on a layer above or below the SRAM memory cell. 
     
     
         64 . The device of  claim 1 ,  claim 51  or the invention of any claim herein, further comprising equalization circuitry that provides bit line equalization. 
     
     
         65 . The device of  claim 64  wherein the equalization circuitry includes a first transistor with drain coupled to the local bit line, a second transistor with drain coupled to the local complement bit line, and a third transistor with source coupled to the local bit line and drain coupled to the local complement bit line, wherein gates of the first, the second and the third transistors are coupled together to an equalization enable signal. 
     
     
         66 . The device of  claim 65  wherein the first, the second and the third transistors are PMOS transistors. 
     
     
         67 . The device of  claim 1 ,  claim 51  or the invention of any claim herein, further comprising write recovery circuitry that provides write recovery of the SRAM memory device. 
     
     
         68 . The device of  claim 67  wherein the write recovery circuitry includes a first transistor with drain coupled to the local bit line, a second transistor with drain coupled to the local complement bit line, and a third transistor with source coupled to the local bit line and drain coupled to the local complement bit line, wherein gates of the first, the second and the third transistors are coupled together to a write recovery enable signal. 
     
     
         69 . The device of  claim 68  wherein the first, the second and the third transistors are PMOS transistors. 
     
     
         70 . The device of  claim 1 ,  claim 51  or the invention of any claim herein wherein the pass gate is a write pass gate defining a write path; and further comprising:
 a read pass gate defining a read path. 
 
     
     
         71 . The device of  claim 70 , wherein:
 the write pass gate comprises an NMOS device; and   the read pass gate comprises a PMOS device.   
     
     
         72 . The device of  claim 70 , wherein the write pass gate is configured to be controlled by a write operation signal. 
     
     
         73 . The device of  claim 70 , wherein the read pass gate is configured to be controlled by a read operation signal. 
     
     
         74 . The device of  claim 1 ,  claim 51  or the invention of any claim herein wherein the local bit line and the global bit line are disposed on a top side of the SRAM memory device. 
     
     
         75 . The device of  claim 1 ,  claim 51  or the invention of any claim herein further comprising bit line equalization circuitry. 
     
     
         76 . The device of  claim 1 ,  claim 51  or the invention of any claim herein further comprising write recovery circuitry. 
     
     
         77 . The device of  claim 1 ,  claim 51  or the invention of any claim herein wherein the memory cells comprise 6T memory cell(s). 
     
     
         78 . The device of  claim 1 ,  claim 51  or the invention of any claim herein wherein the memory cells comprise 8T memory cell(s). 
     
     
         79 . The device of  claim 1 ,  claim 51  or the invention of any claim herein wherein the memory cells comprises 4T memory cell(s) or 1T memory cell(s). 
     
     
         80 . The device of  claim 1 ,  claim 51  or the invention of any claim herein, wherein the SBLs are arranged in a plurality of rows and columns. 
     
     
         81 . The device of  claim 1 ,  claim 51  or the invention of any claim herein further comprising a sense amplifier coupled to the global bit line and/or the local bit line. 
     
     
         82 . The device of  claim 1 ,  claim 51  or the invention of any claim herein further comprising a data driver coupled to the global bit line and/or the local bit line. 
     
     
         83 . The device of  claim 1 ,  claim 51  or the invention of any claim herein wherein a capacitance of the global bit line is less than a capacitance of a comparable global bit line to which the memory cell is directly coupled. 
     
     
         84 . The device of  claim 1 ,  claim 51  or the invention of any claim herein wherein a memory cell active current is as large as an active current of a comparable global bit line to which the memory cell is directly coupled. 
     
     
         85 . The device of  claim 1 ,  claim 51  or the invention of any claim herein wherein an effective global bit line length is less than an effective global bit line length of a comparable global bit line to which the memory cell is directly coupled. 
     
     
         86 . A Sectioned Bit Line (SBL) of an SRAM memory device, the SBL comprising:
 a local bit line;   a memory cell connected to the local bit line; and   a pass gate coupled to the local bit line;   wherein the pass gate is configured to be coupled to a global bit line.   
     
     
         87 . The SBL of  claim 86 , wherein a drain of the pass gate is coupled to the local bit line. 
     
     
         88 . The SBL of  claim 86  wherein the pass gate is a write pass gate defining a write path. 
     
     
         89 . The SBL of  claim 88  wherein the write pass gate is an NMOS device. 
     
     
         90 . The SBL of  claim 86  further comprising a read pass gate defining a read path. 
     
     
         91 . The SBL of  claim 90  wherein the read pass gate is an PMOS device. 
     
     
         92 . The SBL of  claim 86 , wherein the pass gate is a write pass gate defining a write path; and further comprising:
 a read pass gate defining a read path.   
     
     
         93 . The SBL of  claim 92 , wherein:
 the write pass gate comprises an NMOS device; and   the read pass gate comprises a PMOS device.   
     
     
         94 . The SBL of  claim 88  or  claim 93 , wherein the write pass gate is configured to be controlled by a write operation signal. 
     
     
         95 . The SBL of  claim 90  or  claim 93 , wherein the read pass gate is configured to be controlled by a read operation signal. 
     
     
         96 . The device of  claim 1 ,  claim 51  or the invention of any claim herein wherein NMOS transistors are utilized for both the read pass gates and the write pass gates. 
     
     
         97 . The device of  claim 1 ,  claim 51  or the invention of any claim herein wherein PMOS transistors are utilized for both the read pass gates and the write pass gates. 
     
     
         98 . The device of  claim 1 ,  claim 51  or the invention of any claim herein wherein NMOS transistors and PMOS transistors are utilized for both the read pass gates and the write pass gates. 
     
     
         99 . The device of  claim 1   claim 51  or the invention of any claim herein further comprising a complementary pass gate cell including read pass gate circuitry, which includes first transistors with gates connected to the local bit line and complement local bit line and sources coupled to drains of second transistors that have gates coupled to the read pass enable signal, and write pass gate circuitry, which includes transistors with drains coupled to the local bit line and complement local bit line, sources connected to the local data line(s) and gates connected to the write pass enable signal. 
     
     
         100 . An SRAM memory device comprising:
 a global bit line;   a complement global bit line, inverse of the global bit line;   a sectioned bit line (SBL) comprising:
 a local bit line; 
 one or more memory cells connected to the local bit line; 
 a complement local bit line connected to the memory cell; 
 a pass gate coupled to the local bit line; and 
 a pass gate coupled to the complement local bit line; 
   wherein pass gates of SBLs are configured to connect and isolate the sectioned bit line(s) and the global bit line(s).   
     
     
         101 . An SRAM memory device comprising:
 a global bit line;   a plurality of sectioned bit lines (SBLs) each comprising:
 a bit line; 
 one or more memory cells connected to the bit line; 
 a complement bit line connected to the memory cell; and 
 a pass gate coupled to the bit line. 
   
     
     
         102 . The SRAM of  claim 101  wherein pass gates of the SBLs are configured to connect and/or isolate the SBLs and the global bit line. 
     
     
         103 . A method of SRAM operation comprising:
 accessing a plurality of sectioned bit lines, the sectioned bit lines being sections of a global bit line, each sectioned bit line comprising a bit line, one or more memory cells connected to the bit line, a complement bit line connected to the memory cell, and a pass gate coupled to the bit line;   passing data/signals to or from memory cells within the sectioned bit line via the pass gates, wherein the pass gates are configured to connect and isolate the sectioned bit lines and the global bit line.   
     
     
         104 . A method of SRAM operation comprising:
 reading/writing data to one or more of a plurality of sectioned bit lines consistent with any claim, configuration and/or aspect of the disclosure herein.   
     
     
         105 . A method of operating a local section bit line (LSBL) of an SRAM comprising:
 accessing a plurality of sectioned bit lines, the sectioned bit lines being sections of a global bit line, each sectioned bit line comprising a bit line, one or more memory cells connected to the bit line, a complement bit line connected to the memory cell, and a pass gate coupled to the bit line; and   operating the pass gates to connect and/or isolate the sectioned bit lines and the global bit lines.   
     
     
         106 . The method of  claim 105  or the invention of any claim herein, wherein the one or more memory cells comprise two or more LSBLs arranged in direction along the bit line (Y direction). 
     
     
         107 . The method of  claim 105  or the invention of any claim herein, wherein the one or more memory cells comprise at least one LSBL arranged in a direction of a word line (X direction). 
     
     
         108 . The method of  claim 105  or the invention of any claim herein, further comprising:
 operating at least one local sense amplifier and/or at least one local data driver for selection by X and Y addresses. 
 
     
     
         109 . The method of  claim 105  or the invention of any claim herein, further comprising:
 decoding multiple level columns on the global bit line. 
 
     
     
         110 . The method of  claim 105  or the invention of any claim herein, further comprising:
 performing read/write operations using the global bit line, wherein the global bit line is arranged in a same direction as the local bit line(s). 
 
     
     
         111 . The method of  claim 105  or the invention of any claim herein, further comprising:
 amplifying a signal on the local sense line using at least one multiple level sense amplifier, wherein the at least one multiple level sense amplifier is coupled to at least one global bit line and/or the sectioned bit lines. 
 
     
     
         112 . The method of  claim 105  or the invention of any claim herein, further comprising:
 driving data via a multiple level data driver, wherein the multiple level data driver is coupled to at least one global bit line and/or the sectioned bit lines. 
 
     
     
         113 . The method of  claim 105  or the invention of any claim herein, further comprising:
 amplifying a signal on the global bit line via a single global bit line sense amplifier, wherein the single global bit line sense amplifier is coupled to one or more of the local section bit lines (LSBLs). 
 
     
     
         114 . The method of  claim 105  or the invention of any claim herein, wherein the global bit lines, local sense amplifier enable lines, and/or local data driver enable lines are arranged on memory cells in a same direction as the local bit lines. 
     
     
         115 . The method of  claim 105  or the invention of any claim herein, wherein a local sense amplifier enable line and/or a local data driver enable line are arranged as Y direction decoding of the global bit line. 
     
     
         116 . The method of  claim 105  or the invention of any claim herein, further comprising:
 selecting memory cells via local select (LS) lines, wherein the LS lines are configured as a function of X direction decoding. 
 
     
     
         117 . The method of  claim 105  or the invention of any claim herein, wherein one or more local select (LS) lines and/or one or more local pass gate enable lines are configured in a word line direction. 
     
     
         118 . A method of SRAM operation comprising the steps of:
 accessing a plurality of sectioned bit lines, the sectioned bit lines being sections of a global bit line, each sectioned bit line comprising a bit line, one or more memory cells connected to the bit line, a complement bit line connected to the memory cell, and a pass gate coupled to the bit line;   passing data/signals to or from memory cells within the sectioned bit line via the pass gates; and   operating the pass gates to connect and/or isolate the sectioned bit lines and the global bit lines.   
     
     
         119 . The method of  claim 118  further comprising emulating delay of the global bit line via a dummy global bit line, wherein the dummy global bit line is arranged along or in a comparable path of the global bit line. 
     
     
         120 . The method of  claim 118  or the invention of any claim herein, wherein delay is emulated for better timing tracking. 
     
     
         121 . The method of  claim 118  or the invention of any claim herein, further comprising:
 determining an estimated delay on a global bit line via measurement of emulated delay information on the dummy global bit line. 
 
     
     
         122 . The method of  claim 118  or the invention of any claim herein, further comprising:
 performing read/write operations using the global bit lines, wherein at least one of the global bit lines is formed in/on one or more layers above the memory cell and/or on one or more layers below the memory cell. 
 
     
     
         123 . The method of  claim 118  or the invention of any claim herein, further comprising:
 controlling operation of the SRAM via the control signal lines, wherein at least one of the control signal lines is formed on one or more layers above the memory cell and/or on one or more layers below the memory cell. 
 
     
     
         124 . An SRAM memory device comprising:
 a local section bit line including:
 a plurality of sectioned bit lines (SBLs), each comprising:
 a local bit line; 
 one or more memory cells connected to the local bit line; 
 a local complement bit line connected to the memory cell; & 
 a pass gate coupled to the local bit line; 
 
 a local shared sense amplifier; 
 a local shared data driver; 
 a global bit line; 
   wherein the pass gates are configured to connect and/or isolate the sectioned bit line and local sense line.   
     
     
         125 . The device of  claim 124  wherein the local sense amplifier is configured to amplify a signal on a local sense line and provide an output to the global bit line. 
     
     
         126 . An SRAM memory device comprising:
 a local section bit line including:
 a plurality of sectioned bit lines (SBLs), each comprising:
 a local bit line; 
 one or more memory cells connected to the local bit line; 
 a local complement bit line connected to the memory cell; & 
 a pass gate coupled to the local bit line; 
 
 a local shared sense amplifier; 
 a local shared data driver; 
 a global bit line; and 
   a dummy global bit line that is arranged along or in a comparable path of the global bit line;   wherein the pass gates are configured to connect and/or isolate the sectioned bit line and local sense line.   
     
     
         127 . The device of  claim 126  wherein the local sense amplifier is configured to amplify a signal on a local sense line and provide an output to the global bit line. 
     
     
         128 . The invention of any claim herein wherein one or more of: local bit lines and power buses are formed in metal  2 , word lines and power buses are formed in metal  3 , and/or global bit lines, control signal lines and power buses are formed in metal  4 . 
     
     
         129 . The invention of  claim 128  or other claims herein wherein improved tracking is provided in relation to control signal(s) associated with such layering/structures, such as against sense amplifier enable signal(s) and SBL selection signals for SRAMs. 
     
     
         130 . A method of SRAM operation, the method comprising:
 performing one or more steps of SRAM operation involving features or functioning of  claim 1 , and/or of other claims herein, and/or consistent with one or more aspects of this disclosure.   
     
     
         131 . A method of fabricating the SRAM device of  claim 1 , and/or of other claims herein, and/or consistent with one or more aspects this disclosure. 
     
     
         132 . A method of fabricating an SRAM device, the method comprising:
 forming transistors onto one or more substrates;   forming interconnects, including multiple metallization layers and/or interconnects between the transistors; and   connecting the transistors and/or other components wherein an SRAM device of  claim 1 , and/or of other claims herein, and/or consistent with one or more aspects of this disclosure is provided.   
     
     
         133 . A method of fabricating an SRAM device, the method comprising:
 forming elements including transistors onto one or more substrates;   forming interconnects, including multiple metallization layers and/or interconnects between the transistors, wherein one or more of: local bit lines and power buses are formed in metal  2 , word lines and power buses are formed in metal  3 , and/or global bit lines, control signal lines and power buses are formed in metal  4 ; and   connecting the transistors and/or other components wherein an SRAM device according to  claim 1 , and/or according to other claims herein, and/or consistent with one or more aspects of this disclosure is provided.   
     
     
         134 . A method of fabricating an SRAM device, the method comprising:
 forming elements including transistors onto one or more substrates;   forming interconnects, including multiple metallization layers and/or interconnects between the transistors, wherein structures/layers are formed consistent with  FIGS. 15A-15D ; and   connecting the transistors and/or other components wherein an SRAM device according to  claim 1 , and/or according to other claims herein, and/or consistent with one or more aspects of this disclosure is provided.   
     
     
         135 . The method of any of  claims 131 - 134  wherein the fabricating includes one or more CMOS fabrication process(es) and/or CMOS process technologies.