Inventor · disambiguated record
Young Way Teh
Also filed as: TEH YOUNG W · TEH YOUNG WAY
25 granted patents·6 pending applications·567 citations·filing 2000–2022
96Inventor score
Files withCHARTERED SEMICONDUCTOR MFG13IBM5GLOBALFOUNDRIES SG PTE LTD3SAMSUNG ELECTRONICS CO LTD2AJMERA ATUL C1
Top patents by PatentIndex Score
31 records- 0198US7759206B2Methods of forming semiconductor devices using embedded L-shape spacersIBM·Filed 2005·Granted Jul 20, 2010·118 cites·9 claims
- 0297US7867835B2Integrated circuit system for suppressing short channel effectsCHARTERED SEMICONDUCTOR MFG·Filed 2008·Granted Jan 11, 2011·116 cites·20 claims
- 0394US7297584B2Methods of fabricating semiconductor devices having a dual stress linerSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Nov 20, 2007·34 cites·12 claims
- 0493US6406975B1Method for fabricating an air gap shallow trench isolation (STI) structureCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Jun 18, 2002·84 cites·18 claims
- 0593US6380106B1Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structuresCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Apr 30, 2002·84 cites·11 claims
- 0691US7445978B2Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOSCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Nov 4, 2008·22 cites·31 claims
- 0786US6649517B2Copper metal structure for the reduction of intra-metal capacitanceCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Nov 18, 2003·31 cites·26 claims
- 0884US7977185B2Method and apparatus for post silicide spacer removalIBM·Filed 2005·Granted Jul 12, 2011·9 cites·14 claims
- 0984US7256084B2Composite stress spacerCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Aug 14, 2007·12 cites·19 claims
- 1080US7785950B2Dual stress memory technique method and related structureIBM·Filed 2005·Granted Aug 31, 2010·9 cites·13 claims
- 1180US7531401B2Method for improved fabrication of a semiconductor using a stress proximity technique processIBM·Filed 2007·Granted May 12, 2009·7 cites·18 claims
- 1277US7883953B2Method for transistor fabrication with optimized performanceFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Feb 8, 2011·7 cites·18 claims
- 1373US6815823B2Copper metal structure for the reduction of intra-metal capacitanceCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Nov 9, 2004·13 cites·5 claims
- 1472US7993997B2Poly profile engineering to modulate spacer induced stress for device enhancementGLOBALFOUNDRIES SG PTE LTD·Filed 2007·Granted Aug 9, 2011·3 cites·24 claims
- 1571US8624329B2Spacer-less low-K dielectric processesLEE YONG MENG·Filed 2009·Granted Jan 7, 2014·5 cites·18 claims
- 1670US7307320B2Differential mechanical stress-producing regions for integrated circuit field effect transistorsSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Dec 11, 2007·4 cites·26 claims
- 1769US7999325B2Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOSGLOBALFOUNDRIES SG PTE LTD·Filed 2008·Granted Aug 16, 2011·3 cites·20 claims
- 1868US7615427B2Spacer-less low-k dielectric processesCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Nov 10, 2009·3 cites·20 claims
- 1964US8563394B2Integrated circuit structure having substantially planar N-P step height and methods of formingLI WEIPENG·Filed 2011·Granted Oct 22, 2013·2 cites·15 claims
- 2051US2008029823A1Semiconductor Device Having a Dual Stress Liner and Light Exposure Apparatus for Forming the Dual Stress LinerCHARTERED SEMICONDUCTOR MFG·Filed 2007·Application pending·0 cites
- 2150US12266702B2Flash memory devices with thickened source/drain silicideGLOBALFOUNDRIES SG PTE LTD·Filed 2022·Granted Apr 1, 2025·0 cites·20 claims
- 2250US8853796B2High-K metal gate deviceTEH YOUNG WAY·Filed 2011·Granted Oct 7, 2014·1 cites·26 claims
- 2347US2013256766A1Spacer and process to enhance the strain in the channel with stress linerIBM·Filed 2013·Application pending·0 cites
- 2445US2009315115A1Implantation for shallow trench isolation (STI) formation and for stress for transistor performance enhancementCHARTERED SEMICONDUCTOR MFG·Filed 2008·Application pending·0 cites
- 2545US2008315317A1Semiconductor system having complementary strained channelsCHARTERED SEMICONDUCTOR MFG·Filed 2007·Application pending·0 cites
- 2644US8519445B2Poly profile engineering to modulate spacer induced stress for device enhancementHO VINCENT·Filed 2011·Granted Aug 27, 2013·0 cites·20 claims
- 2742US8664717B2Semiconductor device with an oversized local contact as a Faraday shieldLIU YANXIANG·Filed 2012·Granted Mar 4, 2014·0 cites·23 claims
- 2842US2008142897A1Integrated circuit system having strained transistorCHARTERED SEMICONDUCTOR MFG·Filed 2006·Application pending·0 cites
- 2941US8461009B2Spacer and process to enhance the strain in the channel with stress linerAJMERA ATUL C·Filed 2006·Granted Jun 11, 2013·0 cites·16 claims
- 3040US2008044967A1Integrated circuit system having strained transistorCHARTERED SEMICONDUCTOR MFG·Filed 2006·Application pending·0 cites
- 3139US8106462B2Balancing NFET and PFET performance using straining layersCHEN XIANGDONG·Filed 2010·Granted Jan 31, 2012·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →