Spacer and process to enhance the strain in the channel with stress liner

Abstract

Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer composed of a first oxide and first nitride layer is applied to a gate electrode on a substrate, and a second spacer composed of a second oxide and second nitride layer is applied. Deep implanting of source and drain in the substrate occurs, and removal of the second nitride, second oxide, and first nitride layers.

What is claimed: 
     
         1 . A spacer for enhancing strain in a channel, comprising:
 a first spacer composed of an first oxide couplable to a gate electrode and first nitride layer coupled to the first oxide layer; and   a second spacer composed of a second oxide coupled to the first oxide layer and a second nitride layer coupled to the second oxide layer,   wherein the first and second nitride layers and the second oxide layer are removable to form an L-shaped oxide spacer.   
     
     
         2 . The spacer in accordance with  claim 1 , wherein the first oxide layer is formed by gate reoxidation. 
     
     
         3 . The spacer in accordance with  claim 2 , wherein the first oxide layer has a thickness of 1-5 nm. 
     
     
         4 . The spacer in accordance with  claim 1 , wherein the first nitride layer has a thickness of 10-15 nm. 
     
     
         5 . An integrated circuit, comprising:
 a gate electrode formed on a substrate;   an L-shaped oxide spacer arranged adjacent the gate electrode; and   a stress liner deposited over the gate electrode and the L-shaped spacer.   
     
     
         6 . The integrated circuit in accordance with  claim 5 , wherein a vertical extent of the L-shaped oxide spacer has a thickness between 1-5 nm. 
     
     
         7 . The integrated circuit in accordance with  claim 5 , wherein the L-shaped spacer is formed by a first oxide/nitride spacer and a second oxide/nitride spacer, in which the second oxide/nitride spacer and the nitride of the first oxide/nitride spacer are removed. 
     
     
         8 . The integrated circuit in accordance with  claim 5 , wherein the L-shaped oxide layer is formed by removing nitride from an oxide/nitride spacer. 
     
     
         9 . The integrated circuit in accordance with  claim 5 , wherein a source and drain are formed through deep implantation in the substrate. 
     
     
         10 . The integrated circuit in accordance with  claim 9 , wherein silicide is formed after removing nitride from an oxide/nitride spacer. 
     
     
         11 . The integrated circuit in accordance with  claim 9 , wherein silicide is formed before removing nitride from an oxide/nitride spacer. 
     
     
         12 . The integrated circuit in accordance with  claim 5 , wherein the gate electrode is formed by a poly gate etch.