Inventor · disambiguated record
Sharath Raghava
Also filed as: RAGHAVA SHARATH
13 granted patents·5 pending applications·40 citations·filing 2003–2025
88Inventor score
Top patents by PatentIndex Score
18 records- 0194US10649927B2Dual in-line memory module (DIMM) programmable accelerator cardINTEL CORP·Filed 2018·Granted May 12, 2020·16 cites·15 claims
- 0287US12204441B2Flushing cache lines involving persistent memoryINTEL CORP·Filed 2020·Granted Jan 21, 2025·2 cites·18 claims
- 0385US12417319B2Multi-chip secure and programmable systems and methodsLATTICE SEMICONDUCTOR CORP·Filed 2023·Granted Sep 16, 2025·2 cites·20 claims
- 0485US9607714B2Hardware command training for memory using write leveling mechanismNVIDIA CORP·Filed 2012·Granted Mar 28, 2017·12 cites·20 claims
- 0578US12237831B2Network-on-chip (NOC) with flexible data widthINTEL CORP·Filed 2023·Granted Feb 25, 2025·0 cites·16 claims
- 0674US9824772B2Hardware chip select training for memory using read commandsNVIDIA CORP·Filed 2012·Granted Nov 21, 2017·4 cites·20 claims
- 0774US2025117319A1Flushing Cache Lines Involving Persistent MemoryALTERA CORP·Filed 2024·Application pending·0 cites
- 0874US2025167786A1Network-on-chip (noc) with flexible data widthALTERA CORP·Filed 2025·Application pending·0 cites
- 0972US11700002B2Network-on-chip (NOC) with flexible data widthINTEL CORP·Filed 2021·Granted Jul 11, 2023·0 cites·20 claims
- 1069US11342918B2Network-on-chip (NOC) with flexible data widthINTEL CORP·Filed 2020·Granted May 24, 2022·0 cites·20 claims
- 1169US2024028544A1Inter-die communication of programmable logic devicesINTEL CORP·Filed 2023·Application pending·0 cites
- 1268US9368169B2Hardware chip select training for memory using write leveling mechanismNVIDIA CORP·Filed 2012·Granted Jun 14, 2016·4 cites·20 claims
- 1364US10790827B2Network-on-chip (NOC) with flexible data widthINTEL CORP·Filed 2018·Granted Sep 29, 2020·0 cites·20 claims
- 1456US11789883B2Inter-die communication of programmable logic devicesINTEL CORP·Filed 2018·Granted Oct 17, 2023·0 cites·20 claims
- 1547US9378169B2Method and system for changing bus direction in memory systemsNVIDIA CORP·Filed 2012·Granted Jun 28, 2016·0 cites·20 claims
- 1645US7143304B2Method and apparatus for enhancing the speed of a synchronous busSUN MICROSYSTEMS INC·Filed 2003·Granted Nov 28, 2006·0 cites·28 claims
- 1737US2018018118A1Power management in scenarios that handle asynchronous stimulusQUALCOMM INC·Filed 2016·Application pending·0 cites
- 1833US2014181452A1Hardware command training for memory using read commandsNVIDIA CORP·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →