Inter-die communication of programmable logic devices

Abstract

An integrated circuit device may include a first network on chip (NOC) circuit configured to receive a set of data and transfer the set of data to a first node of the first NOC circuitry. The first node is configured to transfer the set of data to a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device.

What is claimed is: 
     
         1 . An integrated circuit device, comprising:
 a first network on chip (NOC) circuit configurable to:
 receive a communication packet comprising a set of data; and 
 transfer the communication packet to a first node of the first NOC circuit, wherein the first node comprises a first protocol translator configurable to translate a first protocol associated with the first NOC circuit into a second protocol associated with an interconnection resource configurable for off-die communication. 
   
     
     
         2 . The integrated circuit device of  claim 1 , wherein the first node is configurable to directly transfer the communication packet to a second node of a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device. 
     
     
         3 . The integrated circuit device of  claim 2 , wherein the second node comprises a second protocol translator configurable to translate the second protocol associated with the interconnection resource into a third protocol associated with the second NOC circuit. 
     
     
         4 . The integrated circuit device of  claim 2 , wherein the communication packet comprises data regarding a plurality of nodes associated with the first NOC circuit and the second NOC circuit that the set of data is routed through. 
     
     
         5 . The integrated circuit device of  claim 4 , wherein the communication packet comprises a string of virtual functions defining an order in which the set of data is to be processed, wherein the first node is configurable to directly transfer the communication packet to the second node based at least in part on the string of virtual functions. 
     
     
         6 . The integrated circuit device of  claim 1 , wherein the communication packet comprises a virtual function identifier corresponding to a portion of the integrated circuit device configured to process the set of data after the first node. 
     
     
         7 . The integrated circuit device of  claim 1 , wherein the first node is configurable to transfer the communication packet to a second node of a second NOC circuit of an additional integrated circuit device via a central router, wherein the central router is positioned between the integrated circuit device and the additional integrated circuit device. 
     
     
         8 . The integrated circuit device of  claim 1 , comprising a second NOC circuit, wherein the communication packet comprises data regarding a plurality of nodes associated with the first NOC circuit and the second NOC circuit that the set of data is routed through. 
     
     
         9 . The integrated circuit device of  claim 1 , wherein the first protocol translator is implemented as hard logic associated with the first node. 
     
     
         10 . A system, comprising:
 a first programmable logic device comprising:
 a first portion associated with a first function block configurable to process a set of data; and 
 first network on chip (NOC) circuitry configurable to:
 receive a communication packet comprising the set of data and a string of virtual functions, wherein the string of virtual functions comprises a first virtual function identifier associated with the first function block and a second virtual function identifier associated with a second function block; and 
 transfer the communication packet to a first node of the first NOC circuitry based at least in part on the string of virtual functions; and 
 
   a second programmable logic device comprising:
 second NOC circuitry configurable to:
 receive the communication packet via the first node and a second node of the second NOC circuitry; and 
 transfer the set of data to a second portion associated with the second function block to process the set of data. 
 
   
     
     
         11 . The system of  claim 10 , wherein the communication packet comprises at least one node between the first function block and the second function block. 
     
     
         12 . The system of  claim 10 , wherein the string of virtual functions defines an order in which the set of data is to be processed. 
     
     
         13 . The system of  claim 10 , comprising a central router positioned separate from and located between the first programmable logic device and the second programmable logic device, wherein the central router is configurable to transfer the set of data between the first programmable logic device, the second programmable logic device based at least in part on the string of virtual functions. 
     
     
         14 . The system of  claim 13 , wherein the central router is configurable to directly transfer the set of data from the first node to the second node without processing the set of data. 
     
     
         15 . The system of  claim 10 , comprising a central router configurable to receive the communication packet from the second node and directly transfer the communication packet to a third node of third NOC circuitry of a third programmable logic device. 
     
     
         16 . The system of  claim 10 , wherein the first function block and the second function block are configurable to implement a protocol translator via soft logic. 
     
     
         17 . A system, comprising:
 a plurality of programmable logic devices on different respective dies, wherein respective programmable logic devices of the plurality of programmable logic devices comprise:
 a first accelerator associated with a first virtual function identifier and configurable to process a set of data; and 
 one or more nodes configurable to:
 receive a communication packet from the first accelerator comprising a string of virtual functions defining order in which the set of data is to be processed and the set of data; and 
 transfer the set of data to a second accelerator of a different programmable logic device of the plurality of programmable logic devices based on the string of virtual functions. 
 
   
     
     
         18 . The system of  claim 17 , comprising a semaphore system comprising a register configurable to be updated in response to the first accelerator processing the set of data. 
     
     
         19 . The system of  claim 17 , wherein a first node of the one or more nodes comprises a first protocol translator, wherein the first node is configurable to receive the communication packet from the first accelerator, wherein the first protocol translator is configurable to translate the set of data of the communication packet from a first protocol associated with the first accelerator to a second protocol associated with an input/output port of the each respective programmable logic device. 
     
     
         20 . The system of  claim 17 , wherein the string of virtual functions comprises the first virtual function identifier associated with the first accelerator and a second virtual function identifier associated with the second accelerator.