Inventor · disambiguated record
Mehul D. Shroff
Also filed as: SHROFF MEHUL · SHROFF MEHUL D · SHROFF MEHUL DILIPKUMAR
117 granted patents·11 pending applications·795 citations·filing 1998–2024
99Inventor score
Top patents by PatentIndex Score
128 records- 0197US8536006B2Logic and non-volatile memory (NVM) integrationSHROFF MEHUL D·Filed 2011·Granted Sep 17, 2013·34 cites·20 claims
- 0297US8536007B2Non-volatile memory cell and logic transistor integrationHALL MARK D·Filed 2012·Granted Sep 17, 2013·32 cites·18 claims
- 0397US8524557B1Integration technique using thermal oxide select gate dielectric for select gate and replacement gate for logicHALL MARK D·Filed 2013·Granted Sep 3, 2013·34 cites·20 claims
- 0497US8399310B2Non-volatile memory and logic circuit process integrationSHROFF MEHUL D·Filed 2010·Granted Mar 19, 2013·36 cites·10 claims
- 0597US8389365B2Non-volatile memory and logic circuit process integrationSHROFF MEHUL D·Filed 2011·Granted Mar 5, 2013·35 cites·20 claims
- 0696US7439134B1Method for process integration of non-volatile memory cell transistors with transistors of another typeFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Oct 21, 2008·50 cites·20 claims
- 0793US8716089B1Integrating formation of a replacement gate transistor and a non-volatile memory cell having thin film storageHALL MARK D·Filed 2013·Granted May 6, 2014·18 cites·20 claims
- 0891US9082824B2Method for forming an electrical connection between metal layersREBER DOUGLAS M·Filed 2013·Granted Jul 14, 2015·13 cites·9 claims
- 0991US8601430B1Device matching tool and methods thereofSHROFF MEHUL D·Filed 2012·Granted Dec 3, 2013·13 cites·20 claims
- 1089US9455220B2Apparatus and method for placing stressors on interconnects within an integrated circuit device to manage electromigration failuresSHROFF MEHUL D·Filed 2014·Granted Sep 27, 2016·8 cites·9 claims
- 1188US9112056B1Method for forming a split-gate deviceSHROFF MEHUL D·Filed 2014·Granted Aug 18, 2015·9 cites·20 claims
- 1288US8946000B2Method for forming an integrated circuit having a programmable fuseFREESCALE SEMICONDUCTOR INC·Filed 2013·Granted Feb 3, 2015·8 cites·19 claims
- 1388US8569816B2Isolated capacitors within shallow trench isolationSHROFF MEHUL D·Filed 2011·Granted Oct 29, 2013·10 cites·21 claims
- 1488US6515343B1Metal-to-metal antifuse with non-conductive diffusion barrierQUICKLOGIC CORP·Filed 1998·Granted Feb 4, 2003·86 cites·21 claims
- 1587US10038081B1Substrate contacts for a transistorNXP USA INC·Filed 2017·Granted Jul 31, 2018·5 cites·20 claims
- 1687US8595667B1Via placement and electronic circuit design processing method and electronic circuit design utilizing sameSHROFF MEHUL D·Filed 2012·Granted Nov 26, 2013·10 cites·6 claims
- 1787US6583043B2Dielectric between metal structures and method thereforMOTOROLA INC·Filed 2001·Granted Jun 24, 2003·58 cites·9 claims
- 1887US6500750B1Semiconductor device and method of formationMOTOROLA INC·Filed 2000·Granted Dec 31, 2002·59 cites·19 claims
- 1986US8713498B2Method and system for physical verification using network segment currentSHROFF MEHUL D·Filed 2011·Granted Apr 29, 2014·10 cites·17 claims
- 2085US8510695B1Techniques for electromigration stress determination in interconnects of an integrated circuitDEMIRCAN ERTUGRUL·Filed 2012·Granted Aug 13, 2013·10 cites·20 claims
- 2184US7491630B2Undoped gate poly integration for improved gate patterning and cobalt silicide extendibilityFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Feb 17, 2009·11 cites·20 claims
- 2283US8906764B2Non-volatile memory (NVM) and logic integrationSHROFF MEHUL D·Filed 2012·Granted Dec 9, 2014·7 cites·20 claims
- 2382US8756559B2Systems and methods for determining aging damage for semiconductor devicesSHROFF MEHUL D·Filed 2012·Granted Jun 17, 2014·9 cites·18 claims
- 2481US9515006B23D device packaging using through-substrate postsFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Dec 6, 2016·5 cites·20 claims
- 2581US9472418B2Method for forming a split-gate deviceHALL MARK D·Filed 2014·Granted Oct 18, 2016·4 cites·20 claims
- 2681US8793632B2Techniques for electromigration stress determination in interconnects of an integrated circuitFREESCALE SEMICONDUCTOR INC·Filed 2013·Granted Jul 29, 2014·6 cites·20 claims
- 2781US6509209B1Method of forming a metal-to-metal antifuse with non-conductive diffusion barrierQUICKLOGIC CORP·Filed 2000·Granted Jan 21, 2003·28 cites·8 claims
- 2879US9466569B2Though-substrate vias (TSVs) and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Oct 11, 2016·4 cites·18 claims
- 2979US7511360B2Semiconductor device having stressors and method for formingFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Mar 31, 2009·6 cites·12 claims
- 3078US9716141B2Applications for nanopillar structuresFREESCALE SEMICONDUCTOR INC·Filed 2015·Granted Jul 25, 2017·2 cites·18 claims
- 3178US7741221B2Method of forming a semiconductor device having dummy featuresFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Jun 22, 2010·6 cites·19 claims
- 3278US7670760B2Treatment for reduction of line edge roughnessFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Mar 2, 2010·6 cites·19 claims
- 3377US8884241B2Incident capacitive sensorHALL MARK D·Filed 2011·Granted Nov 11, 2014·4 cites·21 claims
- 3477US8832624B1Multi-layer process-induced damage tracking and remediationSHROFF MEHUL D·Filed 2013·Granted Sep 9, 2014·4 cites·20 claims
- 3577US8694926B2Techniques for checking computer-aided design layers of a device to reduce the occurrence of missing deck rulesREBER DOUGLAS M·Filed 2012·Granted Apr 8, 2014·4 cites·20 claims
- 3676US9818642B2Method of forming inter-level dielectric structures on semiconductor devicesFREESCALE SEMICONDUCTOR INC·Filed 2015·Granted Nov 14, 2017·2 cites·16 claims
- 3776US9111865B2Method of making a logic transistor and a non-volatile memory (NVM) cellSHROFF MEHUL D·Filed 2012·Granted Aug 18, 2015·4 cites·20 claims
- 3876US8872255B2Semiconductor devices with non-volatile memory cellsFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Oct 28, 2014·2 cites·20 claims
- 3975US9087913B2Integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logicHALL MARK D·Filed 2013·Granted Jul 21, 2015·4 cites·20 claims
- 4073US9443804B2Capping layer interface interruption for stress migration mitigationSHROFF MEHUL D·Filed 2013·Granted Sep 13, 2016·3 cites·17 claims
- 4173US7951695B2Method for reducing plasma discharge damage during processingFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted May 31, 2011·4 cites·18 claims
- 4272US9443041B2Simulation system and method for testing a simulation of a device against one or more violation rulesSHROFF MEHUL·Filed 2012·Granted Sep 13, 2016·5 cites·20 claims
- 4372US9202930B2Memory with discrete storage elementsLOIKO KONSTANTIN V·Filed 2011·Granted Dec 1, 2015·3 cites·10 claims
- 4472US8728886B2Integrating formation of a replacement gate transistor and a non-volatile memory cell using a high-k dielectricHALL MARK D·Filed 2012·Granted May 20, 2014·3 cites·20 claims
- 4572US8707231B2Method and system for derived layer checking for semiconductor device designREBER DOUGLAS M·Filed 2012·Granted Apr 22, 2014·3 cites·18 claims
- 4671US8741719B1Integrating formation of a logic transistor and a non-volatile memory cell using a partial replacement gate techniqueHALL MARK D·Filed 2013·Granted Jun 3, 2014·3 cites·20 claims
- 4771US8658497B2Non-volatile memory (NVM) and logic integrationSHROFF MEHUL D·Filed 2012·Granted Feb 25, 2014·3 cites·14 claims
- 4871US8564044B2Non-volatile memory and logic circuit process integrationSHROFF MEHUL D·Filed 2011·Granted Oct 22, 2013·3 cites·18 claims
- 4969US8877568B2Methods of making logic transistors and non-volatile memory cellsSHROFF MEHUL D·Filed 2013·Granted Nov 4, 2014·2 cites·19 claims
- 5069US7510922B2Spacer T-gate structure for CoSi2 extendibilityFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Mar 31, 2009·4 cites·20 claims
Showing the top 50 of 128 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →