Inventor · disambiguated record
Joshua W. Bowman
Also filed as: BOWMAN JOSHUA · BOWMAN JOSHUA W · BOWMAN JOSHUA WAYNE
34 granted patents·2 pending applications·28 citations·filing 2015–2021
94Inventor score
Top patents by PatentIndex Score
36 records- 0195US11880682B2Systolic array with efficient input reduction and extended array performanceAMAZON TECH INC·Filed 2021·Granted Jan 23, 2024·5 cites·21 claims
- 0284US9639418B2Parity protection of a registerIBM·Filed 2015·Granted May 2, 2017·4 cites·20 claims
- 0383US12423058B2Systolic array with input reduction to multiple reduced inputsAMAZON TECH INC·Filed 2021·Granted Sep 23, 2025·1 cites·20 claims
- 0482US10936321B2Instruction chainingIBM·Filed 2019·Granted Mar 2, 2021·3 cites·20 claims
- 0582US9921833B2Determining of validity of speculative load data after a predetermined period of time in a multi-slice processorIBM·Filed 2015·Granted Mar 20, 2018·3 cites·11 claims
- 0681US10248426B2Direct register restore mechanism for distributed history buffersIBM·Filed 2016·Granted Apr 2, 2019·3 cites·17 claims
- 0780US10949213B2Logical register recovery within a processorIBM·Filed 2018·Granted Mar 16, 2021·2 cites·20 claims
- 0877US9959123B2Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessorIBM·Filed 2015·Granted May 1, 2018·2 cites·7 claims
- 0972US10379867B2Asynchronous flush and restore of distributed history bufferIBM·Filed 2017·Granted Aug 13, 2019·1 cites·20 claims
- 1071US11144364B2Supporting speculative microprocessor instruction executionIBM·Filed 2019·Granted Oct 12, 2021·1 cites·18 claims
- 1171US10949205B2Implementation of execution compression of instructions in slice target register file mapperIBM·Filed 2018·Granted Mar 16, 2021·1 cites·20 claims
- 1269US10545765B2Multi-level history buffer for transaction memory in a microprocessorIBM·Filed 2017·Granted Jan 28, 2020·1 cites·20 claims
- 1367US10719056B2Merging status and control data in a reservation stationIBM·Filed 2016·Granted Jul 21, 2020·1 cites·20 claims
- 1464US11360779B2Logical register recovery within a processorIBM·Filed 2020·Granted Jun 14, 2022·0 cites·20 claims
- 1558US12182691B1Increasing performance of computational array acceleratorsAMAZON TECH INC·Filed 2021·Granted Dec 31, 2024·0 cites·20 claims
- 1658US11301254B2Instruction streaming using state migrationIBM·Filed 2019·Granted Apr 12, 2022·0 cites·20 claims
- 1757US11061681B2Instruction streaming using copy select vectorIBM·Filed 2019·Granted Jul 13, 2021·0 cites·20 claims
- 1856US11093282B2Register file write using pointersIBM·Filed 2019·Granted Aug 17, 2021·0 cites·17 claims
- 1953US10956158B2System and handling of register data in processorsIBM·Filed 2019·Granted Mar 23, 2021·0 cites·15 claims
- 2053US10248421B2Operation of a multi-slice processor with reduced flush and restore latencyIBM·Filed 2016·Granted Apr 2, 2019·0 cites·6 claims
- 2153US10241790B2Operation of a multi-slice processor with reduced flush and restore latencyIBM·Filed 2015·Granted Mar 26, 2019·0 cites·12 claims
- 2252US10740140B2Flush-recovery bandwidth in a processorIBM·Filed 2018·Granted Aug 11, 2020·0 cites·20 claims
- 2352US9928073B2Determining of validity of speculative load data after a predetermined period of time in a multi-slice processorIBM·Filed 2016·Granted Mar 27, 2018·0 cites·6 claims
- 2452US9858078B2Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessorIBM·Filed 2015·Granted Jan 2, 2018·0 cites·13 claims
- 2551US11194578B2Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessorIBM·Filed 2018·Granted Dec 7, 2021·0 cites·18 claims
- 2651US10909034B2Issue queue snooping for asynchronous flush and restore of distributed history bufferIBM·Filed 2017·Granted Feb 2, 2021·0 cites·20 claims
- 2751US10489253B2On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessorIBM·Filed 2017·Granted Nov 26, 2019·0 cites·20 claims
- 2850US11403109B2Steering a history buffer entry to a specific recovery port during speculative flush recovery lookup in a processorIBM·Filed 2018·Granted Aug 2, 2022·0 cites·17 claims
- 2950US11068267B2High bandwidth logical register flush recoveryIBM·Filed 2019·Granted Jul 20, 2021·0 cites·20 claims
- 3048US12333274B2Data-type-aware clock-gatingAMAZON TECH INC·Filed 2020·Granted Jun 17, 2025·0 cites·20 claims
- 3148US11188332B2System and handling of register data in processorsIBM·Filed 2019·Granted Nov 30, 2021·0 cites·17 claims
- 3244US2020019405A1Multiple Level History Buffer for Transaction Memory SupportIBM·Filed 2018·Application pending·0 cites
- 3343US10740107B2Operation of a multi-slice processor implementing load-hit-store handlingIBM·Filed 2016·Granted Aug 11, 2020·0 cites·17 claims
- 3443US10445100B2Broadcasting messages between execution slices for issued instructions indicating when execution results are readyIBM·Filed 2016·Granted Oct 15, 2019·0 cites·17 claims
- 3541US10318294B2Operation of a multi-slice processor implementing dependency accumulation instruction sequencingIBM·Filed 2016·Granted Jun 11, 2019·0 cites·17 claims
- 3635US2018004527A1Operation of a multi-slice processor implementing prioritized dependency chain resolutionIBM·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →