Inventor · disambiguated record
Gideon Intrater
Also filed as: INTRATER GIDEON · INTRATER GIDEON D · INTRATER GIDEON DAVID
46 granted patents·1 pending application·770 citations·filing 1992–2021
98Inventor score
Files withNAT SEMICONDUCTOR CORP20ADESTO TECHNOLOGIES CORP12MIPS TECH INC4INTRATER GIDEON DAVID3ADESTO TECH CORP2
Top patents by PatentIndex Score
47 records- 0191US10636480B2Concurrent read and reconfigured write operations in a memory deviceADESTO TECHNOLOGIES CORP·Filed 2016·Granted Apr 28, 2020·10 cites·18 claims
- 0290US9812200B2Concurrent read and write operations in a serial flash deviceADESTO TECH CORP·Filed 2015·Granted Nov 7, 2017·12 cites·20 claims
- 0390US8145882B1Apparatus and method for processing template based user defined instructionsKISHORE KARAGADA RAMARAO·Filed 2006·Granted Mar 27, 2012·54 cites·6 claims
- 0486US10275372B1Cached memory structure and operationADESTO TECHNOLOGIES CORP·Filed 2018·Granted Apr 30, 2019·4 cites·20 claims
- 0586US9922684B2Memory device ultra-deep power-down mode exit controlADESTO TECHNOLOGIES CORP·Filed 2017·Granted Mar 20, 2018·8 cites·18 claims
- 0686US6836833B1Apparatus and method for discovering a scratch pad memory configurationMIPS TECH INC·Filed 2002·Granted Dec 28, 2004·43 cites·23 claims
- 0786US5684948AMemory management circuit which provides simulated privilege levelsNAT SEMICONDUCTOR CORP·Filed 1995·Granted Nov 4, 1997·216 cites·10 claims
- 0883US9812183B2Read latency reduction in a memory deviceADESTO TECH CORP·Filed 2016·Granted Nov 7, 2017·5 cites·6 claims
- 0981US10031869B1Cached memory structure and operationADESTO TECHNOLOGIES CORP·Filed 2015·Granted Jul 24, 2018·3 cites·20 claims
- 1079US10726888B2Read latency reduction in a memory deviceADESTO TECHNOLOGIES CORP·Filed 2019·Granted Jul 28, 2020·3 cites·20 claims
- 1177US10290334B2Read latency reduction in a memory deviceADESTO TECHNOLOGIES CORP·Filed 2017·Granted May 14, 2019·3 cites·20 claims
- 1276US10409505B2Ultra-deep power down mode control in a memory deviceADESTO TECHNOLOGIES CORP·Filed 2016·Granted Sep 10, 2019·2 cites·20 claims
- 1376US5249286ASelectively locking memory locations within a microprocessor's on-chip cacheNAT SEMICONDUCTOR CORP·Filed 1992·Granted Sep 28, 1993·70 cites·22 claims
- 1471US8924749B2Software controlled power limiting in USB to SATA bridgeINTRATER GIDEON DAVID·Filed 2010·Granted Dec 30, 2014·3 cites·27 claims
- 1571US5491828AIntegrated data processing system having CPU core and parallel independently operating DSP module utilizing successive approximation analog to digital and PWM for parallel disconnectNAT SEMICONDUCTOR CORP·Filed 1994·Granted Feb 13, 1996·27 cites·1 claims
- 1669US8291125B2Speculative read-ahead for improving system throughputINTRATER GIDEON DAVID·Filed 2011·Granted Oct 16, 2012·4 cites·24 claims
- 1769US6065078AMulti-processor element provided with hardware for software debuggingNAT SEMICONDUCTOR CORP·Filed 1998·Granted May 16, 2000·63 cites·22 claims
- 1868US10613763B2Memory device having multiple read buffers for read latency reductionADESTO TECHNOLOGIES CORP·Filed 2017·Granted Apr 7, 2020·1 cites·20 claims
- 1967US5630153AIntegrated digital signal processor/general purpose CPU with shared internal memoryNAT SEMICONDUCTOR CORP·Filed 1994·Granted May 13, 1997·44 cites·10 claims
- 2065US5872960AIntegrated circuit having CPU core operable for switching between two independent asynchronous clock sources of different frequencies while the CPU continues executing instructionsNAT SEMICONDUCTOR CORP·Filed 1996·Granted Feb 16, 1999·22 cites·2 claims
- 2165US5822779AMicroprocessor-based data processing apparatus that commences a next overlapping cycle when a ready signal is detected not to be activeNAT SEMICONDUCTOR CORP·Filed 1997·Granted Oct 13, 1998·54 cites·2 claims
- 2261US8489803B2Efficient use of flash memory in flash drivesINTRATER GIDEON DAVID·Filed 2009·Granted Jul 16, 2013·2 cites·20 claims
- 2361US5600821ADistributed directory for information stored on audio quality memory devicesNAT SEMICONDUCTOR CORP·Filed 1993·Granted Feb 4, 1997·20 cites·28 claims
- 2460US11094375B2Concurrent read and reconfigured write operations in a memory deviceADESTO TECHNOLOGIES CORP·Filed 2020·Granted Aug 17, 2021·0 cites·20 claims
- 2557US11366774B2Memory latency reduction in XIP modeADESTO TECHNOLOGIES CORP·Filed 2020·Granted Jun 21, 2022·0 cites·18 claims
- 2657US5592677AIntegrated data processing system including CPU core and parallel, independently operating DSP moduleNAT SEMICONDUCTOR CORP·Filed 1994·Granted Jan 7, 1997·15 cites·4 claims
- 2755US9064076B1User interface for facilitation of high level generation of processor extensionsBRAUN GUNNAR·Filed 2006·Granted Jun 23, 2015·2 cites·33 claims
- 2853US11704258B2Latency reduction in SPI flash memory devicesDIALOG SEMICONDUCTOR US INC·Filed 2021·Granted Jul 18, 2023·0 cites·18 claims
- 2953US6961819B2Method and apparatus for redirection of operations between interfacesMIPS TECH INC·Filed 2002·Granted Nov 1, 2005·4 cites·45 claims
- 3051US5613149AIntegrated data processing system utilizing successive approximation analog to digital conversion and PWM for parallel disconnectNAT SEMICONDUCTOR CORP·Filed 1995·Granted Mar 18, 1997·11 cites·2 claims
- 3149US8151093B2Software programmable hardware state machinesBANERJEE SOUMYA·Filed 2006·Granted Apr 3, 2012·0 cites·24 claims
- 3248US11681352B2Standby current reduction in memory devicesADESTO TECHNOLOGIES CORP·Filed 2020·Granted Jun 20, 2023·0 cites·14 claims
- 3348US7509456B2Apparatus and method for discovering a scratch pad memory configurationMIPS TECH INC·Filed 2004·Granted Mar 24, 2009·0 cites·16 claims
- 3448US2012221838A1Software programmable hardware state machinesBANERJEE SOUMYA·Filed 2012·Application pending·0 cites
- 3547US12510950B2Low power standby mode for memory devicesGLOBALFOUNDRIES US INC·Filed 2021·Granted Dec 30, 2025·0 cites·20 claims
- 3647US5596764ADebug mechanism for parallel-operating DSP module and CPU coreNAT SEMICONDUCTOR CORP·Filed 1994·Granted Jan 21, 1997·9 cites·5 claims
- 3745US10509589B2Support for improved throughput in a memory deviceADESTO TECHNOLOGIES CORP·Filed 2015·Granted Dec 17, 2019·0 cites·40 claims
- 3845US7634619B2Method and apparatus for redirection of operations between interfacesMIPS TECH INC·Filed 2005·Granted Dec 15, 2009·0 cites·25 claims
- 3943US5590357AIntegrated CPU core and parallel, independently operating DSP module and time-critical core priority schemeNAT SEMICONDUCTOR CORP·Filed 1994·Granted Dec 31, 1996·7 cites·2 claims
- 4042US5566308AProcessor core which provides a linear extension of an addressable memory spaceNAT SEMICONDUCTOR CORP·Filed 1994·Granted Oct 15, 1996·15 cites·14 claims
- 4141US5649208AMechanism for handling non-maskable interrupt requests received from different sourcesNAT SEMICONDUCTOR CORP·Filed 1995·Granted Jul 15, 1997·6 cites·2 claims
- 4241US5638306ATesting hooks for testing an integrated data processing systemNAT SEMICONDUCTOR CORP·Filed 1996·Granted Jun 10, 1997·6 cites·9 claims
- 4341US5603017AParallel integrated circuit having DSP module and CPU core operable for switching between two independent asynchronous clock sources while the system continues executing instructionsNAT SEMICONDUCTOR CORP·Filed 1994·Granted Feb 11, 1997·5 cites·1 claims
- 4440US5606714AIntegrated data processing system including CPU core and parallel, independently operating DSP module and having multiple operating modesNAT SEMICONDUCTOR CORP·Filed 1995·Granted Feb 25, 1997·6 cites·1 claims
- 4532US5915266AProcessor core which provides a linear extension of an addressable memory spaceNAT SEMICONDUCTOR CORP·Filed 1996·Granted Jun 22, 1999·4 cites·3 claims
- 4631US5446909ABinary multiplication implemented by existing hardware with minor modifications to sequentially designate bits of the operandNAT SEMICONDUCTOR CORP·Filed 1992·Granted Aug 29, 1995·6 cites·6 claims
- 4728USRE40942EIntegrated digital signal processor/general purpose CPU with shared internal memoryNAT SEMICONDUCTOR CORP·Filed 1999·Granted Oct 20, 2009·1 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →