Inventor · disambiguated record
Brian R. Konigsburg
Also filed as: KONIGSBURG BRIAN · KONIGSBURG BRIAN R
43 granted patents·1 pending application·706 citations·filing 1996–2021
98Inventor score
Files withIBM33KONIGSBURG BRIAN R3MICROSOFT TECHNOLOGY LICENSING LLC2EKANADHAM KATTAMURI1GLOBALFOUNDRIES INC1
Top patents by PatentIndex Score
44 records- 0197US9613699B1Memory system with a content addressable superconducting memoryMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2016·Granted Apr 4, 2017·22 cites·20 claims
- 0296US7487334B2Branch encoding before instruction cache writeIBM·Filed 2005·Granted Feb 3, 2009·61 cites·1 claims
- 0394US9405866B1Automating a microarchitecture design exploration environmentIBM·Filed 2015·Granted Aug 2, 2016·13 cites·15 claims
- 0493US9069563B2Reducing store-hit-loads in an out-of-order processorKONIGSBURG BRIAN R·Filed 2011·Granted Jun 30, 2015·32 cites·20 claims
- 0592US9858373B2In-cycle resource sharing for high-level synthesis of microprocessorsIBM·Filed 2015·Granted Jan 2, 2018·11 cites·20 claims
- 0690US8943299B2Operating a stack of information in an information handling systemEKANADHAM KATTAMURI·Filed 2010·Granted Jan 27, 2015·17 cites·23 claims
- 0786US9779803B1Memory circuit with write-bypass portionKONIGSBURG BRIAN·Filed 2017·Granted Oct 3, 2017·21 cites·20 claims
- 0886US5784391ADistributed memory system with ECC and method of operationIBM·Filed 1996·Granted Jul 21, 1998·124 cites·6 claims
- 0985US10685002B2Radix sort acceleration using custom asicIBM·Filed 2017·Granted Jun 16, 2020·3 cites·20 claims
- 1082US9715411B2Techniques for mapping logical threads to physical threads in a simultaneous multithreading data processing systemIBM·Filed 2014·Granted Jul 25, 2017·6 cites·20 claims
- 1182US7237094B2Instruction group formation and mechanism for SMT dispatchIBM·Filed 2004·Granted Jun 26, 2007·33 cites·21 claims
- 1281US11275712B2SIMD controller and SIMD predication schemeNORTHROP GRUMMAN SYSTEMS CORP·Filed 2020·Granted Mar 15, 2022·2 cites·18 claims
- 1380US10545739B2LLVM-based system C compiler for architecture synthesisIBM·Filed 2016·Granted Jan 28, 2020·3 cites·19 claims
- 1480US9928261B2Radix sort acceleration using custom ASICIBM·Filed 2014·Granted Mar 27, 2018·4 cites·11 claims
- 1579US9665674B2Automating a microarchitecture design exploration environmentIBM·Filed 2016·Granted May 30, 2017·2 cites·15 claims
- 1676US9442736B2Techniques for selecting a predicted indirect branch address from global and local cachesGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 13, 2016·4 cites·20 claims
- 1773US6279105B1Pipelined two-cycle branch target address cacheIBM·Filed 1998·Granted Aug 21, 2001·62 cites·16 claims
- 1872US10795683B2Predicting indirect branches using problem branch filtering and pattern cacheIBM·Filed 2014·Granted Oct 6, 2020·3 cites·8 claims
- 1971US9741419B1Memory system with a content addressable superconducting memoryMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2017·Granted Aug 22, 2017·2 cites·20 claims
- 2069US5931957ASupport for out-of-order execution of loads and stores in a processorIBM·Filed 1997·Granted Aug 3, 1999·57 cites·1 claims
- 2165US7426631B2Methods and systems for storing branch information in an address table of a processorIBM·Filed 2005·Granted Sep 16, 2008·2 cites·8 claims
- 2265US5802571AApparatus and method for enforcing data coherency in an information handling system having multiple hierarchical levels of cache memoryIBM·Filed 1996·Granted Sep 1, 1998·44 cites·16 claims
- 2363US6412051B1System and method for controlling a memory array in an information handling systemIBM·Filed 1996·Granted Jun 25, 2002·21 cites·9 claims
- 2461US8635436B2Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stallINDUKURU VENKAT R·Filed 2011·Granted Jan 21, 2014·1 cites·11 claims
- 2560US5805849AData processing system and method for using an unique identifier to maintain an age relationship between executing instructionsIBM·Filed 1997·Granted Sep 8, 1998·36 cites·23 claims
- 2657US6484230B1Method and system for speculatively processing a load instruction before completion of a preceding synchronization instructionIBM·Filed 1998·Granted Nov 19, 2002·32 cites·20 claims
- 2756US6662360B1Method and system for software control of hardware branch prediction mechanism in a data processorIBM·Filed 1999·Granted Dec 9, 2003·31 cites·8 claims
- 2855US9081895B2Identifying and tagging breakpoint instructions for facilitation of software debugIBM·Filed 2013·Granted Jul 14, 2015·0 cites·8 claims
- 2955US6622236B1Microprocessor instruction fetch unit for processing instruction groups having multiple branch instructionsIBM·Filed 2000·Granted Sep 16, 2003·6 cites·24 claims
- 3054US9953044B2Radix sort acceleration using custom ASICIBM·Filed 2015·Granted Apr 24, 2018·0 cites·8 claims
- 3154US9495170B2Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stallIBM·Filed 2013·Granted Nov 15, 2016·0 cites·12 claims
- 3254US7984280B2Storing branch information in an address table of a processorIBM·Filed 2008·Granted Jul 19, 2011·0 cites·6 claims
- 3353US9507891B1Automating a microarchitecture design exploration environmentIBM·Filed 2015·Granted Nov 29, 2016·0 cites·20 claims
- 3453US9170920B2Identifying and tagging breakpoint instructions for facilitation of software debugIBM·Filed 2013·Granted Oct 27, 2015·0 cites·12 claims
- 3552US11838397B2Systems and methods for synchronization of processing elementsKONIGSBURG BRIAN R·Filed 2021·Granted Dec 5, 2023·0 cites·19 claims
- 3651US6286094B1Method and system for optimizing the fetching of dispatch groups in a superscalar processorIBM·Filed 1999·Granted Sep 4, 2001·23 cites·5 claims
- 3750US8943301B2Storing branch information in an address table of a processorKONIGSBURG BRIAN R·Filed 2011·Granted Jan 27, 2015·0 cites·19 claims
- 3849US9524166B2Tracking long GHV in high performance out-of-order superscalar processorsIBM·Filed 2013·Granted Dec 20, 2016·0 cites·17 claims
- 3946US7475223B2Fetch-side instruction dispatch group formationIBM·Filed 2005·Granted Jan 6, 2009·0 cites·17 claims
- 4041US6021467AApparatus and method for processing multiple cache misses to a single cache lineIBM·Filed 1996·Granted Feb 1, 2000·13 cites·16 claims
- 4140US6385719B1Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessorIBM·Filed 1999·Granted May 7, 2002·12 cites·14 claims
- 4239US2012005462A1Hardware Assist for Optimizing Code During ProcessingHALL RONALD P·Filed 2010·Application pending·0 cites
- 4338US9946512B2Adaptive radix external in-place radix sortIBM·Filed 2015·Granted Apr 17, 2018·0 cites·17 claims
- 4432US6304959B1Simplified method to generate BTAGs in a decode unit of a processing systemIBM·Filed 1999·Granted Oct 16, 2001·3 cites·4 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →