Inventor · disambiguated record
Christopher V. Baiocco
Also filed as: BAIOCCO CHRISTOPHER V · BAIOCCO CHRISTOPHER VINCENT · Baiocco Christopher
14 granted patents·8 pending applications·123 citations·filing 2004–2016
91Inventor score
Top patents by PatentIndex Score
22 records- 0194US9874693B2Method and structure for integrating photonics with CMOsBaiocco Christopher·Filed 2015·Granted Jan 23, 2018·43 cites·34 claims
- 0292US8053301B2CMOS SiGe channel pFET and Si channel nFET devices with minimal STI recessIBM·Filed 2009·Granted Nov 8, 2011·27 cites·14 claims
- 0391US9034748B2Process variability tolerant hard mask for replacement metal gate finFET devicesIBM·Filed 2013·Granted May 19, 2015·13 cites·10 claims
- 0480US7531401B2Method for improved fabrication of a semiconductor using a stress proximity technique processIBM·Filed 2007·Granted May 12, 2009·7 cites·18 claims
- 0577US7883953B2Method for transistor fabrication with optimized performanceFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Feb 8, 2011·7 cites·18 claims
- 0674US7471548B2Structure of static random access memory with stress engineering for stabilityIBM·Filed 2006·Granted Dec 30, 2008·13 cites·1 claims
- 0773US9093495B2Method and structure to reduce FET threshold voltage shift due to oxygen diffusionBAIOCCO CHRISTOPHER VINCENT·Filed 2012·Granted Jul 28, 2015·4 cites·18 claims
- 0869US7521308B2Dual layer stress liner for MOSFETSIBM·Filed 2006·Granted Apr 21, 2009·3 cites·3 claims
- 0961US8629028B2Metal oxide semiconductor field effect transistor (MOSFET) gate terminationIBM·Filed 2013·Granted Jan 14, 2014·1 cites·17 claims
- 1052US7081397B2Trench sidewall passivation for lateral RIE in a selective silicon-on-insulator process flowIBM·Filed 2004·Granted Jul 25, 2006·5 cites·20 claims
- 1150US2013140670A1Structure and method for reduction of vt-w effect in high-k metal gate devicesIBM·Filed 2013·Application pending·0 cites
- 1248US9431289B2Method and structure to reduce FET threshold voltage shift due to oxygen diffusionGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 30, 2016·0 cites·4 claims
- 1347US2013256766A1Spacer and process to enhance the strain in the channel with stress linerIBM·Filed 2013·Application pending·0 cites
- 1444US2012187522A1Structure and method for reduction of vt-w effect in high-k metal gate devicesAQUILINO MICHAEL V·Filed 2011·Application pending·0 cites
- 1542US2008124859A1Methods of Forming CMOS Integrated Circuits Using Gate Sidewall Spacer Reduction TechniquesSUN MIN CHUL·Filed 2006·Application pending·0 cites
- 1641US8704332B2Metal oxide semiconductor field effect transistor (MOSFET) gate terminationBAIOCCO CHRISTOPHER V·Filed 2012·Granted Apr 22, 2014·0 cites·10 claims
- 1741US8461009B2Spacer and process to enhance the strain in the channel with stress linerAJMERA ATUL C·Filed 2006·Granted Jun 11, 2013·0 cites·16 claims
- 1840US9754071B1Integrated circuit (IC) design analysis and feature extractionGLOBALFOUNDRIES INC·Filed 2016·Granted Sep 5, 2017·0 cites·18 claims
- 1940US2008124880A1Fet structure using disposable spacer and stress inducing layerCHARTERED SEMICONDUCTOR MFG·Filed 2006·Application pending·0 cites
- 2039US2007254420A1Source/drain implantation and channel strain transfer using different sized spacers and related semiconductor deviceIBM·Filed 2006·Application pending·0 cites
- 2136US2013032897A1Mosfet gate electrode employing arsenic-doped silicon-germanium alloy layerIBM·Filed 2011·Application pending·0 cites
- 2234US2009166757A1Stress engineering for sram stabilityIBM·Filed 2007·Application pending·0 cites
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